From cae5cb0cabc4847781fb359d98f7e1d9c7a7909e Mon Sep 17 00:00:00 2001 From: =?utf8?q?Jouni=20H=C3=B6gander?= Date: Mon, 5 Sep 2022 13:23:55 +0300 Subject: [PATCH] drm/i915/psr: Disable PSR2 when SDP is sent on prior line MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Selective update doesn't work if SU start address is 0 and start/end SDP is configured to be sent prior to SU start/end lines. PSR2 has to be disabled in this case for Alder Lake. HSDES: 22012279113 Cc: Mika Kahola Cc: José Roberto de Souza Signed-off-by: Jouni Högander Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20220905102355.176622-3-jouni.hogander@intel.com Reviewed-by: Mika Kahola --- drivers/gpu/drm/i915/display/intel_psr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 6f03bf16d6f4..90d7cdd743be 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -811,7 +811,8 @@ static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d if ((hblank_ns - req_ns) > 100) return true; - if (DISPLAY_VER(dev_priv) < 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b) + /* Not supported <13 / Wa_22012279113:adl-p */ + if (DISPLAY_VER(dev_priv) <= 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b) return false; crtc_state->req_psr2_sdp_prior_scanline = true; -- 2.34.1