From cab5b3861dad8c6bc9dea80d2bd66e560ef63ed7 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Tue, 20 Aug 2019 18:43:14 -0400 Subject: [PATCH] radeonsi/gfx10: fix tessellation for the legacy pipeline ported from PAL Acked-by: Pierre-Eric Pelloux-Prayer --- src/gallium/drivers/radeonsi/si_state_shaders.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index c9800c0..22c54d3 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -1308,6 +1308,16 @@ static void si_emit_shader_vs(struct si_context *sctx) if (initial_cdw != sctx->gfx_cs->current.cdw) sctx->context_roll = true; + + /* Required programming for tessellation. (legacy pipeline only) */ + if (sctx->chip_class == GFX10 && + shader->selector->type == PIPE_SHADER_TESS_EVAL) { + radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL, + SI_TRACKED_VGT_GS_ONCHIP_CNTL, + S_028A44_ES_VERTS_PER_SUBGRP(250) | + S_028A44_GS_PRIMS_PER_SUBGRP(126) | + S_028A44_GS_INST_PRIMS_IN_SUBGRP(126)); + } } /** -- 2.7.4