From ca4a3b308e89bc514cd7a610f3f94255e447c8a7 Mon Sep 17 00:00:00 2001 From: ciceron Date: Sat, 21 Jul 2001 11:39:13 +0000 Subject: [PATCH] * config/m68hc11/m68hc11.md ("andqi3"): Accept d as second operand. ("iorqi3"): Likewise. ("xorqi3"): Likewise. ("*addhi3"): Fix constraint to avoid reloading in a soft register. ("*subhi3_sp): Likewise. ("*subhi3"): Likewise. ("extendhisi2"): Accept D, X and Y as source operand to avoid reload problems. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@44229 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 11 +++++++++++ gcc/config/m68hc11/m68hc11.md | 22 +++++++++++----------- 2 files changed, 22 insertions(+), 11 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5421fd0..b5c95a9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2001-07-21 Stephane Carrez + + * config/m68hc11/m68hc11.md ("andqi3"): Accept d as second operand. + ("iorqi3"): Likewise. + ("xorqi3"): Likewise. + ("*addhi3"): Fix constraint to avoid reloading in a soft register. + ("*subhi3_sp): Likewise. + ("*subhi3"): Likewise. + ("extendhisi2"): Accept D, X and Y as source operand to avoid + reload problems. + 2001-07-21 Nathan Sidwell * doc/tm.texi: Remove DEFAULT_VTABLE_THUNKS. diff --git a/gcc/config/m68hc11/m68hc11.md b/gcc/config/m68hc11/m68hc11.md index e75f1ad..8392c2c 100644 --- a/gcc/config/m68hc11/m68hc11.md +++ b/gcc/config/m68hc11/m68hc11.md @@ -1552,7 +1552,7 @@ (define_insn "extendhisi2" [(set (match_operand:SI 0 "register_operand" "=D,D,D") - (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "m,!r,0")))] + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "m,!r,dA")))] "" "* { @@ -2283,7 +2283,7 @@ (define_insn "*addhi3" [(set (match_operand:HI 0 "hard_reg_operand" "=A,d,!A,d*A,!d") (plus:HI (match_operand:HI 1 "general_operand" "%0,0,0,0,0") - (match_operand:HI 2 "general_operand" "N,i,I,umi*A*d,!*d*w")))] + (match_operand:HI 2 "general_operand" "N,i,I,mi*A*d,!u*d*w")))] "TARGET_M6811" "* { @@ -2621,7 +2621,7 @@ (define_insn "*subhi3_sp" [(set (match_operand:HI 0 "stack_register_operand" "=w,w") (minus:HI (match_operand:HI 1 "register_operand" "0,0") - (match_operand:HI 2 "general_operand" "uim*d,!*A"))) + (match_operand:HI 2 "general_operand" "im*d,!u*A"))) (clobber (match_scratch:HI 3 "=A*d,A*d"))] "" "* @@ -2670,9 +2670,9 @@ (define_insn "*subhi3" - [(set (match_operand:HI 0 "register_operand" "=d,*A") - (minus:HI (match_operand:HI 1 "register_operand" "0,0") - (match_operand:HI 2 "general_operand" "uim*A*d,uim*d*A")))] + [(set (match_operand:HI 0 "register_operand" "=d,*A,d*A") + (minus:HI (match_operand:HI 1 "register_operand" "0,0,0") + (match_operand:HI 2 "general_operand" "im*A*d,im*d*A,!u")))] "" "* { @@ -3100,7 +3100,7 @@ (define_insn "andqi3" [(set (match_operand:QI 0 "register_operand" "=d,!u,d,d,?*A,?*A,!*q") (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,0,0") - (match_operand:QI 2 "general_operand" "i,i,!um,?*A,i!um,?*A,i!um*A")))] + (match_operand:QI 2 "general_operand" "i,i,!um,?*A,!ium,?*A*d,!ium*A")))] "" "* { @@ -3207,7 +3207,7 @@ (define_insn "iorqi3" [(set (match_operand:QI 0 "register_operand" "=d,!u,d,d,?*A,?*A,!*q") (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,0,0") - (match_operand:QI 2 "general_operand" "i,i,!um,!*A,i!um,!*A,i!um*A")))] + (match_operand:QI 2 "general_operand" "i,i,!um,!*A,!ium,?*A*d,!ium*A")))] "" "* { @@ -3301,9 +3301,9 @@ }") (define_insn "xorqi3" - [(set (match_operand:QI 0 "register_operand" "=d,d,!*u*A,!*u*A,!*q") - (xor:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0") - (match_operand:QI 2 "general_operand" "ium,!*A,ium,!*A,ium*A*u")))] + [(set (match_operand:QI 0 "register_operand" "=d,d,d,?*A,?*A,!*q") + (xor:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,0") + (match_operand:QI 2 "general_operand" "i,!um,!*A,!ium,?*A*d,!ium*A")))] "" "* { -- 2.7.4