From c9d1b58b272e272fc7121929e2d0e0755ea1656e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 1 Apr 2021 15:01:36 +0200 Subject: [PATCH] clk: renesas: div6: Switch to .determine_rate() As the .round_rate() callback returns a long clock rate, it cannot return clock rates that do not fit in signed long, but do fit in unsigned long. Hence switch the DIV6 clocks on SH/R-Mobile and R-Car SoCs from the old .round_rate() callback to the newer .determine_rate() callback, which does not suffer from this limitation. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/7fd8c45cd8bf5c6d928ca69c8b669be35b93de09.1617281699.git.geert+renesas@glider.be --- drivers/clk/renesas/clk-div6.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/clk/renesas/clk-div6.c b/drivers/clk/renesas/clk-div6.c index 2920bec..3af65ef 100644 --- a/drivers/clk/renesas/clk-div6.c +++ b/drivers/clk/renesas/clk-div6.c @@ -100,12 +100,14 @@ static unsigned int cpg_div6_clock_calc_div(unsigned long rate, return clamp(div, 1U, 64U); } -static long cpg_div6_clock_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int cpg_div6_clock_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { - unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate); + unsigned int div = cpg_div6_clock_calc_div(req->rate, + req->best_parent_rate); - return *parent_rate / div; + req->rate = req->best_parent_rate / div; + return 0; } static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate, @@ -166,7 +168,7 @@ static const struct clk_ops cpg_div6_clock_ops = { .get_parent = cpg_div6_clock_get_parent, .set_parent = cpg_div6_clock_set_parent, .recalc_rate = cpg_div6_clock_recalc_rate, - .round_rate = cpg_div6_clock_round_rate, + .determine_rate = cpg_div6_clock_determine_rate, .set_rate = cpg_div6_clock_set_rate, }; -- 2.7.4