From c96a7f88b92c8c572a67edf87d4fea64caa5401a Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Tue, 24 Jun 2014 10:47:52 +0000 Subject: [PATCH] InstCombine: Disable umul.with.overflow recognition for vectors. It doesn't make a lot on most targets and the code isn't ready for it. PR20113. llvm-svn: 211583 --- llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp | 6 +++++- llvm/test/Transforms/InstCombine/overflow-mul.ll | 11 +++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp index 639d831..f204eeb 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp @@ -2042,9 +2042,13 @@ static Instruction *ProcessUAddIdiom(Instruction &I, Value *OrigAddV, /// replacement required. static Instruction *ProcessUMulZExtIdiom(ICmpInst &I, Value *MulVal, Value *OtherVal, InstCombiner &IC) { + // Don't bother doing this transformation for pointers, don't do it for + // vectors. + if (!isa(MulVal->getType())) + return nullptr; + assert(I.getOperand(0) == MulVal || I.getOperand(1) == MulVal); assert(I.getOperand(0) == OtherVal || I.getOperand(1) == OtherVal); - assert(isa(MulVal->getType())); Instruction *MulInstr = cast(MulVal); assert(MulInstr->getOpcode() == Instruction::Mul); diff --git a/llvm/test/Transforms/InstCombine/overflow-mul.ll b/llvm/test/Transforms/InstCombine/overflow-mul.ll index 04019ae..cbb2f5f 100644 --- a/llvm/test/Transforms/InstCombine/overflow-mul.ll +++ b/llvm/test/Transforms/InstCombine/overflow-mul.ll @@ -162,3 +162,14 @@ entry: ret i32 %retval } +define <4 x i32> @pr20113(<4 x i16> %a, <4 x i16> %b) { +; CHECK-LABEL: @pr20113 +; CHECK-NOT: mul.with.overflow +; CHECK: ret + %vmovl.i.i726 = zext <4 x i16> %a to <4 x i32> + %vmovl.i.i712 = zext <4 x i16> %b to <4 x i32> + %mul.i703 = mul <4 x i32> %vmovl.i.i712, %vmovl.i.i726 + %tmp = icmp sge <4 x i32> %mul.i703, zeroinitializer + %vcgez.i = sext <4 x i1> %tmp to <4 x i32> + ret <4 x i32> %vcgez.i +} -- 2.7.4