From c935232822f83502eb11bdff8e25512269858f27 Mon Sep 17 00:00:00 2001 From: Italo Nicola Date: Thu, 6 Oct 2022 12:20:44 +0000 Subject: [PATCH] rusticl: use 32-bit address format for 32-bit devices Signed-off-by: Italo Nicola Reviewed-by: Karol Herbst Part-of: --- src/gallium/frontends/rusticl/core/kernel.rs | 15 +++++++-- src/gallium/frontends/rusticl/core/program.rs | 3 ++ .../frontends/rusticl/mesa/compiler/clc/spirv.rs | 37 ++++++++++++++++------ 3 files changed, 44 insertions(+), 11 deletions(-) diff --git a/src/gallium/frontends/rusticl/core/kernel.rs b/src/gallium/frontends/rusticl/core/kernel.rs index a7f0a87..927b159 100644 --- a/src/gallium/frontends/rusticl/core/kernel.rs +++ b/src/gallium/frontends/rusticl/core/kernel.rs @@ -523,10 +523,21 @@ fn lower_and_optimize_nir_late( | nir_variable_mode::nir_var_mem_global, Some(glsl_get_cl_type_size_align), ); + + let global_address_format; + let shared_address_format; + if dev.address_bits() == 32 { + global_address_format = nir_address_format::nir_address_format_32bit_global; + shared_address_format = nir_address_format::nir_address_format_32bit_offset; + } else { + global_address_format = nir_address_format::nir_address_format_64bit_global; + shared_address_format = nir_address_format::nir_address_format_32bit_offset_as_64bit; + } + nir.pass2( nir_lower_explicit_io, nir_variable_mode::nir_var_mem_global | nir_variable_mode::nir_var_mem_constant, - nir_address_format::nir_address_format_64bit_global, + global_address_format, ); nir.pass0(nir_lower_system_values); let mut compute_options = nir_lower_compute_system_values_options::default(); @@ -539,7 +550,7 @@ fn lower_and_optimize_nir_late( nir_variable_mode::nir_var_mem_shared | nir_variable_mode::nir_var_function_temp | nir_variable_mode::nir_var_uniform, - nir_address_format::nir_address_format_32bit_offset_as_64bit, + shared_address_format, ); if nir_options.lower_int64_options.0 != 0 { diff --git a/src/gallium/frontends/rusticl/core/program.rs b/src/gallium/frontends/rusticl/core/program.rs index fc501bc..15c4a77 100644 --- a/src/gallium/frontends/rusticl/core/program.rs +++ b/src/gallium/frontends/rusticl/core/program.rs @@ -383,6 +383,7 @@ impl Program { &Vec::new(), get_disk_cache(), dev.cl_features(), + dev.address_bits(), ); d.log = log; @@ -444,6 +445,7 @@ impl Program { headers, get_disk_cache(), dev.cl_features(), + dev.address_bits(), ); d.spirv = spirv; @@ -581,6 +583,7 @@ impl Program { .nir_shader_compiler_options(pipe_shader_type::PIPE_SHADER_COMPUTE), &d.lib_clc, &mut [], + d.address_bits(), ) .unwrap() } diff --git a/src/gallium/frontends/rusticl/mesa/compiler/clc/spirv.rs b/src/gallium/frontends/rusticl/mesa/compiler/clc/spirv.rs index 63963ca..fafa250 100644 --- a/src/gallium/frontends/rusticl/mesa/compiler/clc/spirv.rs +++ b/src/gallium/frontends/rusticl/mesa/compiler/clc/spirv.rs @@ -49,6 +49,7 @@ impl SPIRVBin { headers: &[CLCHeader], cache: &Option, features: clc_optional_features, + address_bits: u32, ) -> (Option, String) { let mut hash_key = None; let has_includes = args.iter().any(|a| a.as_bytes()[0..2] == *b"-I"); @@ -96,7 +97,7 @@ impl SPIRVBin { spirv_version: clc_spirv_version::CLC_SPIRV_VERSION_MAX, features: features, allowed_spirv_extensions: ptr::null(), - address_bits: 64, + address_bits: address_bits, }; let mut msgs: Vec = Vec::new(); let logger = clc_logger { @@ -251,7 +252,22 @@ impl SPIRVBin { } } - fn get_spirv_options(library: bool, clc_shader: *const nir_shader) -> spirv_to_nir_options { + fn get_spirv_options( + library: bool, + clc_shader: *const nir_shader, + address_bits: u32, + ) -> spirv_to_nir_options { + let global_addr_format; + let offset_addr_format; + + if address_bits == 32 { + global_addr_format = nir_address_format::nir_address_format_32bit_global; + offset_addr_format = nir_address_format::nir_address_format_32bit_offset; + } else { + global_addr_format = nir_address_format::nir_address_format_64bit_global; + offset_addr_format = nir_address_format::nir_address_format_32bit_offset_as_64bit; + } + spirv_to_nir_options { create_library: library, environment: nir_spirv_execution_environment::NIR_SPIRV_OPENCL, @@ -275,10 +291,10 @@ impl SPIRVBin { ..Default::default() }, - constant_addr_format: nir_address_format::nir_address_format_64bit_global, - global_addr_format: nir_address_format::nir_address_format_64bit_global, // TODO 32 bit devices - shared_addr_format: nir_address_format::nir_address_format_32bit_offset_as_64bit, - temp_addr_format: nir_address_format::nir_address_format_32bit_offset_as_64bit, + constant_addr_format: global_addr_format, + global_addr_format: global_addr_format, + shared_addr_format: offset_addr_format, + temp_addr_format: offset_addr_format, // default debug: spirv_to_nir_options__bindgen_ty_1::default(), @@ -292,9 +308,10 @@ impl SPIRVBin { nir_options: *const nir_shader_compiler_options, libclc: &NirShader, spec_constants: &mut [nir_spirv_specialization], + address_bits: u32, ) -> Option { let c_entry = CString::new(entry_point.as_bytes()).unwrap(); - let spirv_options = Self::get_spirv_options(false, libclc.get_nir()); + let spirv_options = Self::get_spirv_options(false, libclc.get_nir(), address_bits); let nir = unsafe { spirv_to_nir( @@ -314,10 +331,12 @@ impl SPIRVBin { pub fn get_lib_clc(screen: &PipeScreen) -> Option { let nir_options = screen.nir_shader_compiler_options(pipe_shader_type::PIPE_SHADER_COMPUTE); - let spirv_options = Self::get_spirv_options(true, ptr::null()); + let address_bits = screen.compute_param(pipe_compute_cap::PIPE_COMPUTE_CAP_ADDRESS_BITS); + let spirv_options = Self::get_spirv_options(true, ptr::null(), address_bits); let shader_cache = DiskCacheBorrowed::as_ptr(&screen.shader_cache()); + NirShader::new(unsafe { - nir_load_libclc_shader(64, shader_cache, &spirv_options, nir_options) + nir_load_libclc_shader(address_bits, shader_cache, &spirv_options, nir_options) }) } -- 2.7.4