From c8d3c7ae7426f6b7522bdf656b65ded1db23470c Mon Sep 17 00:00:00 2001 From: "keith.zhao" Date: Fri, 24 Jun 2022 21:55:26 +0800 Subject: [PATCH] riscv:driver:drm:DC8200 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit 1、update dts for vout driver code Signed-off-by:keith.zhao --- arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 4 ++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 13 ++++++++----- 2 files changed, 12 insertions(+), 5 deletions(-) mode change 100644 => 100755 arch/riscv/boot/dts/starfive/jh7110-common.dtsi diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi old mode 100644 new mode 100755 index eaadfeb..3591e82 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -722,6 +722,10 @@ status = "okay"; }; +&mipi_dphy { + status = "disabled"; +}; + &co_process { status = "okay"; }; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 150225a..b45860e 100755 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -1487,14 +1487,15 @@ hdmi_output: hdmi-output { compatible = "verisilicon,hdmi-encoder"; - verisilicon,dss-syscon = <&dssctrl>; - verisilicon,mux-mask = <0x70 0x380>; - verisilicon,mux-val = <0x40 0x280>; + //verisilicon,dss-syscon = <&dssctrl>; + //verisilicon,mux-mask = <0x70 0x380>; + //verisilicon,mux-val = <0x40 0x280>; status = "disabled"; }; dc8200: dc8200@29400000 { compatible = "verisilicon,dc8200"; + verisilicon,dss-syscon = <&dssctrl>;//20220624 panel syscon reg = <0x0 0x29400000 0x0 0x100>, <0x0 0x29400800 0x0 0x2000>, <0x0 0x17030000 0x0 0x1000>; @@ -1520,13 +1521,15 @@ <&clkvout JH7110_U0_DC8200_CLK_CORE>, <&clkvout JH7110_U0_DC8200_CLK_AHB>, <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>, - <&clkgen JH7110_DOM_VOUT_TOP_LCD_CLK>; + <&clkgen JH7110_DOM_VOUT_TOP_LCD_CLK>, + <&hdmitx0_pixelclk>, + <&clkvout JH7110_DC8200_PIX0>; clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc", "noc_disp","noc_isp","noc_stg","vout_src", "top_vout_axi","ahb1","top_vout_ahb", "top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1", "axi_clk","core_clk","vout_ahb", - "vout_top_axi","vout_top_lcd"; + "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0"; resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>, <&rstgen RSTN_U0_DC8200_AXI>, -- 2.7.4