From c8b1c953f6411b1f9a5f2b745d945f5b4a56ea6f Mon Sep 17 00:00:00 2001 From: Fei Peng Date: Wed, 11 Jul 2018 15:55:37 -0700 Subject: [PATCH] Fix VEX.vvvv encoding for AVX.BlendVariable Commit migrated from https://github.com/dotnet/coreclr/commit/a03b08ab38186db8bb30a412bc73165810140119 --- src/coreclr/src/jit/emitxarch.cpp | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/coreclr/src/jit/emitxarch.cpp b/src/coreclr/src/jit/emitxarch.cpp index 7809c50..bdbf335 100644 --- a/src/coreclr/src/jit/emitxarch.cpp +++ b/src/coreclr/src/jit/emitxarch.cpp @@ -293,6 +293,9 @@ bool emitter::IsDstDstSrcAVXInstruction(instruction ins) case INS_unpcklps: case INS_unpckhpd: case INS_unpcklpd: + case INS_vblendvps: + case INS_vblendvpd: + case INS_vpblendvb: case INS_vfmadd132pd: case INS_vfmadd213pd: case INS_vfmadd231pd: @@ -9382,7 +9385,8 @@ BYTE* emitter::emitOutputAM(BYTE* dst, instrDesc* id, code_t code, CnsVal* addc) { regNumber src1 = id->idReg2(); - if ((id->idInsFmt() != IF_RWR_RRD_ARD) && (id->idInsFmt() != IF_RWR_RRD_ARD_CNS)) + if ((id->idInsFmt() != IF_RWR_RRD_ARD) && (id->idInsFmt() != IF_RWR_RRD_ARD_CNS) && + (id->idInsFmt() != IF_RWR_RRD_ARD_RRD)) { src1 = id->idReg1(); } -- 2.7.4