From c8a889fc0e115d40a2d02f32842655f3eadc8fa1 Mon Sep 17 00:00:00 2001 From: Hongyu Wang Date: Wed, 20 Oct 2021 13:13:39 +0800 Subject: [PATCH] i386: Fix wrong codegen for V8HF move without TARGET_AVX512F Since _Float16 type is enabled under sse2 target, returning V8HFmode vector without AVX512F target would generate wrong vmovdqa64 instruction. Adjust ix86_get_ssemov to avoid this. gcc/ChangeLog: PR target/102812 * config/i386/i386.c (ix86_get_ssemov): Adjust HFmode vector move to use the same logic as HImode. gcc/testsuite/ChangeLog: PR target/102812 * gcc.target/i386/pr102812.c: New test. --- gcc/config/i386/i386.c | 15 ++++++++++++--- gcc/testsuite/gcc.target/i386/pr102812.c | 12 ++++++++++++ 2 files changed, 24 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr102812.c diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index e3988f8..299e1ab 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -5399,9 +5399,18 @@ ix86_get_ssemov (rtx *operands, unsigned size, switch (scalar_mode) { case E_HFmode: - opcode = (misaligned_p - ? (TARGET_AVX512BW ? "vmovdqu16" : "vmovdqu64") - : "vmovdqa64"); + if (evex_reg_p) + opcode = (misaligned_p + ? (TARGET_AVX512BW + ? "vmovdqu16" + : "vmovdqu64") + : "vmovdqa64"); + else + opcode = (misaligned_p + ? (TARGET_AVX512BW + ? "vmovdqu16" + : "%vmovdqu") + : "%vmovdqa"); break; case E_SFmode: opcode = misaligned_p ? "%vmovups" : "%vmovaps"; diff --git a/gcc/testsuite/gcc.target/i386/pr102812.c b/gcc/testsuite/gcc.target/i386/pr102812.c new file mode 100644 index 0000000..bad4fa9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr102812.c @@ -0,0 +1,12 @@ +/* PR target/102812 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse4 -mno-avx" } */ +/* { dg-final { scan-assembler-not "vmovdqa64\t" } } */ +/* { dg-final { scan-assembler "movdqa\t" } } */ + +typedef _Float16 v8hf __attribute__((__vector_size__ (16))); + +v8hf t (_Float16 a) +{ + return (v8hf) {a, 0, 0, 0, 0, 0, 0, 0}; +} -- 2.7.4