From c88bf54366f19d849b0b23f1ec6037e10fbc0d05 Mon Sep 17 00:00:00 2001 From: Ahmed Bougacha Date: Thu, 11 Jun 2015 19:30:37 +0000 Subject: [PATCH] [CodeGen] ArrayRef'ize cond/pred in various TII APIs. NFC. llvm-svn: 239553 --- llvm/include/llvm/Target/TargetInstrInfo.h | 13 ++++++------- llvm/lib/CodeGen/TargetInstrInfo.cpp | 5 ++--- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 8 ++++---- llvm/lib/Target/AArch64/AArch64InstrInfo.h | 13 +++++-------- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 10 ++++------ llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 9 ++++----- llvm/lib/Target/BPF/BPFInstrInfo.cpp | 2 +- llvm/lib/Target/BPF/BPFInstrInfo.h | 3 +-- llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 13 ++++++------- llvm/lib/Target/Hexagon/HexagonInstrInfo.h | 16 +++++++--------- llvm/lib/Target/MSP430/MSP430InstrInfo.cpp | 2 +- llvm/lib/Target/MSP430/MSP430InstrInfo.h | 3 +-- llvm/lib/Target/Mips/MipsInstrInfo.cpp | 5 ++--- llvm/lib/Target/Mips/MipsInstrInfo.h | 5 ++--- llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp | 2 +- llvm/lib/Target/NVPTX/NVPTXInstrInfo.h | 2 +- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 17 +++++++---------- llvm/lib/Target/PowerPC/PPCInstrInfo.h | 20 ++++++++------------ llvm/lib/Target/R600/AMDGPUInstrInfo.cpp | 7 +++---- llvm/lib/Target/R600/AMDGPUInstrInfo.h | 4 ++-- llvm/lib/Target/R600/R600InstrInfo.cpp | 13 ++++++------- llvm/lib/Target/R600/R600InstrInfo.h | 10 ++++++---- llvm/lib/Target/Sparc/SparcInstrInfo.cpp | 2 +- llvm/lib/Target/Sparc/SparcInstrInfo.h | 3 +-- llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 5 ++--- llvm/lib/Target/SystemZ/SystemZInstrInfo.h | 6 ++---- llvm/lib/Target/X86/X86InstrInfo.cpp | 8 +++----- llvm/lib/Target/X86/X86InstrInfo.h | 9 +++------ llvm/lib/Target/XCore/XCoreInstrInfo.cpp | 2 +- llvm/lib/Target/XCore/XCoreInstrInfo.h | 3 +-- 30 files changed, 94 insertions(+), 126 deletions(-) diff --git a/llvm/include/llvm/Target/TargetInstrInfo.h b/llvm/include/llvm/Target/TargetInstrInfo.h index 902b99c..c358310 100644 --- a/llvm/include/llvm/Target/TargetInstrInfo.h +++ b/llvm/include/llvm/Target/TargetInstrInfo.h @@ -405,7 +405,7 @@ public: /// merging needs to be disabled. virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, + ArrayRef Cond, DebugLoc DL) const { llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch!"); } @@ -530,7 +530,7 @@ public: /// @param TrueCycles Latency from TrueReg to select output. /// @param FalseCycles Latency from FalseReg to select output. virtual bool canInsertSelect(const MachineBasicBlock &MBB, - const SmallVectorImpl &Cond, + ArrayRef Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const { @@ -554,8 +554,7 @@ public: /// @param FalseReg Virtual register to copy when Cons is false. virtual void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, - unsigned DstReg, - const SmallVectorImpl &Cond, + unsigned DstReg, ArrayRef Cond, unsigned TrueReg, unsigned FalseReg) const { llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!"); } @@ -878,13 +877,13 @@ public: /// It returns true if the operation was successful. virtual bool PredicateInstruction(MachineInstr *MI, - const SmallVectorImpl &Pred) const; + ArrayRef Pred) const; /// Returns true if the first specified predicate /// subsumes the second, e.g. GE subsumes GT. virtual - bool SubsumesPredicate(const SmallVectorImpl &Pred1, - const SmallVectorImpl &Pred2) const { + bool SubsumesPredicate(ArrayRef Pred1, + ArrayRef Pred2) const { return false; } diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp index c809087..20cb396 100644 --- a/llvm/lib/CodeGen/TargetInstrInfo.cpp +++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp @@ -219,9 +219,8 @@ TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { return !isPredicated(MI); } - -bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI, - const SmallVectorImpl &Pred) const { +bool TargetInstrInfo::PredicateInstruction( + MachineInstr *MI, ArrayRef Pred) const { bool MadeChange = false; assert(!MI->isBundle() && diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 6941a6b..69def58 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -255,7 +255,7 @@ unsigned AArch64InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { void AArch64InstrInfo::instantiateCondBranch( MachineBasicBlock &MBB, DebugLoc DL, MachineBasicBlock *TBB, - const SmallVectorImpl &Cond) const { + ArrayRef Cond) const { if (Cond[0].getImm() != -1) { // Regular Bcc BuildMI(&MBB, DL, get(AArch64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB); @@ -272,7 +272,7 @@ void AArch64InstrInfo::instantiateCondBranch( unsigned AArch64InstrInfo::InsertBranch( MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, DebugLoc DL) const { + ArrayRef Cond, DebugLoc DL) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); @@ -369,7 +369,7 @@ static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg, } bool AArch64InstrInfo::canInsertSelect( - const MachineBasicBlock &MBB, const SmallVectorImpl &Cond, + const MachineBasicBlock &MBB, ArrayRef Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const { // Check register classes. @@ -412,7 +412,7 @@ bool AArch64InstrInfo::canInsertSelect( void AArch64InstrInfo::insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DstReg, - const SmallVectorImpl &Cond, + ArrayRef Cond, unsigned TrueReg, unsigned FalseReg) const { MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h index d296768..4c32653 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h @@ -140,17 +140,14 @@ public: bool AllowModify = false) const override; unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, + MachineBasicBlock *FBB, ArrayRef Cond, DebugLoc DL) const override; bool ReverseBranchCondition(SmallVectorImpl &Cond) const override; - bool canInsertSelect(const MachineBasicBlock &, - const SmallVectorImpl &Cond, unsigned, - unsigned, int &, int &, int &) const override; + bool canInsertSelect(const MachineBasicBlock &, ArrayRef Cond, + unsigned, unsigned, int &, int &, int &) const override; void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - DebugLoc DL, unsigned DstReg, - const SmallVectorImpl &Cond, + DebugLoc DL, unsigned DstReg, ArrayRef Cond, unsigned TrueReg, unsigned FalseReg) const override; void getNoopForMachoTarget(MCInst &NopInst) const override; @@ -189,7 +186,7 @@ public: private: void instantiateCondBranch(MachineBasicBlock &MBB, DebugLoc DL, MachineBasicBlock *TBB, - const SmallVectorImpl &Cond) const; + ArrayRef Cond) const; }; /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 9c4b496..93dc423 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -396,7 +396,7 @@ unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { unsigned ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, + ArrayRef Cond, DebugLoc DL) const { ARMFunctionInfo *AFI = MBB.getParent()->getInfo(); int BOpc = !AFI->isThumbFunction() @@ -458,8 +458,7 @@ bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const { } bool ARMBaseInstrInfo:: -PredicateInstruction(MachineInstr *MI, - const SmallVectorImpl &Pred) const { +PredicateInstruction(MachineInstr *MI, ArrayRef Pred) const { unsigned Opc = MI->getOpcode(); if (isUncondBranchOpcode(Opc)) { MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); @@ -479,9 +478,8 @@ PredicateInstruction(MachineInstr *MI, return false; } -bool ARMBaseInstrInfo:: -SubsumesPredicate(const SmallVectorImpl &Pred1, - const SmallVectorImpl &Pred2) const { +bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef Pred1, + ArrayRef Pred2) const { if (Pred1.size() > 2 || Pred2.size() > 2) return false; diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h index c7185fe..1f9e983 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h @@ -116,8 +116,7 @@ public: bool AllowModify = false) const override; unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, + MachineBasicBlock *FBB, ArrayRef Cond, DebugLoc DL) const override; bool @@ -133,10 +132,10 @@ public: } bool PredicateInstruction(MachineInstr *MI, - const SmallVectorImpl &Pred) const override; + ArrayRef Pred) const override; - bool SubsumesPredicate(const SmallVectorImpl &Pred1, - const SmallVectorImpl &Pred2) const override; + bool SubsumesPredicate(ArrayRef Pred1, + ArrayRef Pred2) const override; bool DefinesPredicate(MachineInstr *MI, std::vector &Pred) const override; diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.cpp b/llvm/lib/Target/BPF/BPFInstrInfo.cpp index 28bd0ec..83d14ef 100644 --- a/llvm/lib/Target/BPF/BPFInstrInfo.cpp +++ b/llvm/lib/Target/BPF/BPFInstrInfo.cpp @@ -133,7 +133,7 @@ bool BPFInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, unsigned BPFInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, + ArrayRef Cond, DebugLoc DL) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.h b/llvm/lib/Target/BPF/BPFInstrInfo.h index 4056c2e..ac60188 100644 --- a/llvm/lib/Target/BPF/BPFInstrInfo.h +++ b/llvm/lib/Target/BPF/BPFInstrInfo.h @@ -51,8 +51,7 @@ public: unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, + MachineBasicBlock *FBB, ArrayRef Cond, DebugLoc DL) const override; }; } diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index e566a97..3cb0823 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -159,7 +159,7 @@ findLoopInstr(MachineBasicBlock *BB, int EndLoopOp, unsigned HexagonInstrInfo::InsertBranch( MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, DebugLoc DL) const { + ArrayRef Cond, DebugLoc DL) const { Opcode_t BOpc = Hexagon::J2_jump; Opcode_t BccOpc = Hexagon::J2_jumpt; @@ -1013,7 +1013,7 @@ int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const { bool HexagonInstrInfo:: PredicateInstruction(MachineInstr *MI, - const SmallVectorImpl &Cond) const { + ArrayRef Cond) const { if (Cond.empty() || isEndLoopN(Cond[0].getImm())) { DEBUG(dbgs() << "\nCannot predicate:"; MI->dump();); return false; @@ -1162,8 +1162,8 @@ HexagonInstrInfo::DefinesPredicate(MachineInstr *MI, bool HexagonInstrInfo:: -SubsumesPredicate(const SmallVectorImpl &Pred1, - const SmallVectorImpl &Pred2) const { +SubsumesPredicate(ArrayRef Pred1, + ArrayRef Pred2) const { // TODO: Fix this return false; } @@ -1982,8 +1982,7 @@ bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode) const { (Opcode == Hexagon::J2_jumpf); } -bool HexagonInstrInfo::predOpcodeHasNot( - const SmallVectorImpl &Cond) const { +bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef Cond) const { if (Cond.empty() || !isPredicated(Cond[0].getImm())) return false; return !isPredicatedTrue(Cond[0].getImm()); @@ -1994,7 +1993,7 @@ bool HexagonInstrInfo::isEndLoopN(Opcode_t Opcode) const { Opcode == Hexagon::ENDLOOP1); } -bool HexagonInstrInfo::getPredReg(const SmallVectorImpl &Cond, +bool HexagonInstrInfo::getPredReg(ArrayRef Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const { if (Cond.empty()) diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h index a7ae65e..d0b8a46 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h @@ -69,8 +69,7 @@ public: unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, + MachineBasicBlock *FBB, ArrayRef Cond, DebugLoc DL) const override; bool analyzeCompare(const MachineInstr *MI, @@ -129,7 +128,7 @@ public: bool isBranch(const MachineInstr *MI) const; bool isPredicable(MachineInstr *MI) const override; bool PredicateInstruction(MachineInstr *MI, - const SmallVectorImpl &Cond) const override; + ArrayRef Cond) const override; bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, @@ -149,8 +148,8 @@ public: bool isPredicatedNew(unsigned Opcode) const; bool DefinesPredicate(MachineInstr *MI, std::vector &Pred) const override; - bool SubsumesPredicate(const SmallVectorImpl &Pred1, - const SmallVectorImpl &Pred2) const override; + bool SubsumesPredicate(ArrayRef Pred1, + ArrayRef Pred2) const override; bool ReverseBranchCondition(SmallVectorImpl &Cond) const override; @@ -222,11 +221,10 @@ public: bool NonExtEquivalentExists (const MachineInstr *MI) const; short getNonExtOpcode(const MachineInstr *MI) const; bool PredOpcodeHasJMP_c(Opcode_t Opcode) const; - bool predOpcodeHasNot(const SmallVectorImpl &Cond) const; + bool predOpcodeHasNot(ArrayRef Cond) const; bool isEndLoopN(Opcode_t Opcode) const; - bool getPredReg(const SmallVectorImpl &Cond, - unsigned &PredReg, unsigned &PredRegPos, - unsigned &PredRegFlags) const; + bool getPredReg(ArrayRef Cond, unsigned &PredReg, + unsigned &PredRegPos, unsigned &PredRegFlags) const; int getCondOpcode(int Opc, bool sense) const; }; diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp index 27681aa..72b1780 100644 --- a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp +++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp @@ -262,7 +262,7 @@ bool MSP430InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, unsigned MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, + ArrayRef Cond, DebugLoc DL) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.h b/llvm/lib/Target/MSP430/MSP430InstrInfo.h index f9b25b6..3cf3b1b 100644 --- a/llvm/lib/Target/MSP430/MSP430InstrInfo.h +++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.h @@ -82,8 +82,7 @@ public: unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, + MachineBasicBlock *FBB, ArrayRef Cond, DebugLoc DL) const override; }; diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp index 0839147..bb23cc0 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp +++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp @@ -96,8 +96,7 @@ bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - DebugLoc DL, - const SmallVectorImpl &Cond) const { + DebugLoc DL, ArrayRef Cond) const { unsigned Opc = Cond[0].getImm(); const MCInstrDesc &MCID = get(Opc); MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); @@ -115,7 +114,7 @@ MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, unsigned MipsInstrInfo::InsertBranch( MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, DebugLoc DL) const { + ArrayRef Cond, DebugLoc DL) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.h b/llvm/lib/Target/Mips/MipsInstrInfo.h index 4589535..08efc35 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.h +++ b/llvm/lib/Target/Mips/MipsInstrInfo.h @@ -59,8 +59,7 @@ public: unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, + MachineBasicBlock *FBB, ArrayRef Cond, DebugLoc DL) const override; bool @@ -140,7 +139,7 @@ private: SmallVectorImpl &Cond) const; void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL, - const SmallVectorImpl& Cond) const; + ArrayRef Cond) const; }; /// Create MipsInstrInfo objects. diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp index dabc3be..76d6597 100644 --- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp @@ -248,7 +248,7 @@ unsigned NVPTXInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { unsigned NVPTXInstrInfo::InsertBranch( MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, DebugLoc DL) const { + ArrayRef Cond, DebugLoc DL) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 1 || Cond.size() == 0) && diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h index 9b5d491..179c068 100644 --- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h +++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h @@ -66,7 +66,7 @@ public: unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned InsertBranch( MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, DebugLoc DL) const override; + ArrayRef Cond, DebugLoc DL) const override; unsigned getLdStCodeAddrSpace(const MachineInstr &MI) const { return MI.getOperand(2).getImm(); } diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index b4bb50c..d3bb7a6 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -548,7 +548,7 @@ unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { unsigned PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, + ArrayRef Cond, DebugLoc DL) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); @@ -593,7 +593,7 @@ PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, // Select analysis. bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB, - const SmallVectorImpl &Cond, + ArrayRef Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const { if (!Subtarget.hasISEL()) @@ -634,8 +634,7 @@ bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB, void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc dl, - unsigned DestReg, - const SmallVectorImpl &Cond, + unsigned DestReg, ArrayRef Cond, unsigned TrueReg, unsigned FalseReg) const { assert(Cond.size() == 2 && "PPC branch conditions have two components!"); @@ -1213,9 +1212,8 @@ bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { return !isPredicated(MI); } -bool PPCInstrInfo::PredicateInstruction( - MachineInstr *MI, - const SmallVectorImpl &Pred) const { +bool PPCInstrInfo::PredicateInstruction(MachineInstr *MI, + ArrayRef Pred) const { unsigned OpC = MI->getOpcode(); if (OpC == PPC::BLR || OpC == PPC::BLR8) { if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { @@ -1306,9 +1304,8 @@ bool PPCInstrInfo::PredicateInstruction( return false; } -bool PPCInstrInfo::SubsumesPredicate( - const SmallVectorImpl &Pred1, - const SmallVectorImpl &Pred2) const { +bool PPCInstrInfo::SubsumesPredicate(ArrayRef Pred1, + ArrayRef Pred2) const { assert(Pred1.size() == 2 && "Invalid PPC first predicate"); assert(Pred2.size() == 2 && "Invalid PPC second predicate"); diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h index 7fd076a..b318b17 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h @@ -141,18 +141,14 @@ public: bool AllowModify) const override; unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, + MachineBasicBlock *FBB, ArrayRef Cond, DebugLoc DL) const override; // Select analysis. - bool canInsertSelect(const MachineBasicBlock&, - const SmallVectorImpl &Cond, - unsigned, unsigned, int&, int&, int&) const override; - void insertSelect(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, DebugLoc DL, - unsigned DstReg, - const SmallVectorImpl &Cond, + bool canInsertSelect(const MachineBasicBlock &, ArrayRef Cond, + unsigned, unsigned, int &, int &, int &) const override; + void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, + DebugLoc DL, unsigned DstReg, ArrayRef Cond, unsigned TrueReg, unsigned FalseReg) const override; void copyPhysReg(MachineBasicBlock &MBB, @@ -211,10 +207,10 @@ public: bool isUnpredicatedTerminator(const MachineInstr *MI) const override; bool PredicateInstruction(MachineInstr *MI, - const SmallVectorImpl &Pred) const override; + ArrayRef Pred) const override; - bool SubsumesPredicate(const SmallVectorImpl &Pred1, - const SmallVectorImpl &Pred2) const override; + bool SubsumesPredicate(ArrayRef Pred1, + ArrayRef Pred2) const override; bool DefinesPredicate(MachineInstr *MI, std::vector &Pred) const override; diff --git a/llvm/lib/Target/R600/AMDGPUInstrInfo.cpp b/llvm/lib/Target/R600/AMDGPUInstrInfo.cpp index 64e295f..15a3d54 100644 --- a/llvm/lib/Target/R600/AMDGPUInstrInfo.cpp +++ b/llvm/lib/Target/R600/AMDGPUInstrInfo.cpp @@ -234,10 +234,9 @@ bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const { // TODO: Implement this function return false; } -bool -AMDGPUInstrInfo::SubsumesPredicate(const SmallVectorImpl &Pred1, - const SmallVectorImpl &Pred2) - const { + +bool AMDGPUInstrInfo::SubsumesPredicate(ArrayRef Pred1, + ArrayRef Pred2) const { // TODO: Implement this function return false; } diff --git a/llvm/lib/Target/R600/AMDGPUInstrInfo.h b/llvm/lib/Target/R600/AMDGPUInstrInfo.h index 8fd27a1..86d3962 100644 --- a/llvm/lib/Target/R600/AMDGPUInstrInfo.h +++ b/llvm/lib/Target/R600/AMDGPUInstrInfo.h @@ -125,8 +125,8 @@ public: void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override; bool isPredicated(const MachineInstr *MI) const override; - bool SubsumesPredicate(const SmallVectorImpl &Pred1, - const SmallVectorImpl &Pred2) const override; + bool SubsumesPredicate(ArrayRef Pred1, + ArrayRef Pred2) const override; bool DefinesPredicate(MachineInstr *MI, std::vector &Pred) const override; bool isPredicable(MachineInstr *MI) const override; diff --git a/llvm/lib/Target/R600/R600InstrInfo.cpp b/llvm/lib/Target/R600/R600InstrInfo.cpp index 5f0bdf3..5ef883c 100644 --- a/llvm/lib/Target/R600/R600InstrInfo.cpp +++ b/llvm/lib/Target/R600/R600InstrInfo.cpp @@ -354,7 +354,7 @@ R600InstrInfo::ExtractSrcs(MachineInstr *MI, const DenseMap &PV, unsigned &ConstCount) const { ConstCount = 0; - const SmallVector, 3> Srcs = getSrcs(MI); + ArrayRef> Srcs = getSrcs(MI); const std::pair DummyPair(-1, 0); std::vector > Result; unsigned i = 0; @@ -628,8 +628,7 @@ R600InstrInfo::fitsConstReadLimitations(const std::vector &MIs) if (!isALUInstr(MI->getOpcode())) continue; - const SmallVectorImpl > &Srcs = - getSrcs(MI); + ArrayRef> Srcs = getSrcs(MI); for (unsigned j = 0, e = Srcs.size(); j < e; j++) { std::pair Src = Srcs[j]; @@ -782,7 +781,7 @@ unsigned R600InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, + ArrayRef Cond, DebugLoc DL) const { assert(TBB && "InsertBranch must not be told to insert a fallthrough"); @@ -1000,15 +999,15 @@ R600InstrInfo::DefinesPredicate(MachineInstr *MI, bool -R600InstrInfo::SubsumesPredicate(const SmallVectorImpl &Pred1, - const SmallVectorImpl &Pred2) const { +R600InstrInfo::SubsumesPredicate(ArrayRef Pred1, + ArrayRef Pred2) const { return false; } bool R600InstrInfo::PredicateInstruction(MachineInstr *MI, - const SmallVectorImpl &Pred) const { + ArrayRef Pred) const { int PIdx = MI->findFirstPredOperandIdx(); if (MI->getOpcode() == AMDGPU::CF_ALU) { diff --git a/llvm/lib/Target/R600/R600InstrInfo.h b/llvm/lib/Target/R600/R600InstrInfo.h index d3dc0e5..dee4c2b 100644 --- a/llvm/lib/Target/R600/R600InstrInfo.h +++ b/llvm/lib/Target/R600/R600InstrInfo.h @@ -162,7 +162,9 @@ namespace llvm { bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const override; - unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl &Cond, DebugLoc DL) const override; + unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, + MachineBasicBlock *FBB, ArrayRef Cond, + DebugLoc DL) const override; unsigned RemoveBranch(MachineBasicBlock &MBB) const override; @@ -188,14 +190,14 @@ namespace llvm { bool DefinesPredicate(MachineInstr *MI, std::vector &Pred) const override; - bool SubsumesPredicate(const SmallVectorImpl &Pred1, - const SmallVectorImpl &Pred2) const override; + bool SubsumesPredicate(ArrayRef Pred1, + ArrayRef Pred2) const override; bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override; bool PredicateInstruction(MachineInstr *MI, - const SmallVectorImpl &Pred) const override; + ArrayRef Pred) const override; unsigned int getPredicationCost(const MachineInstr *) const override; diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp index 4b70f16..f87cee4 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp @@ -229,7 +229,7 @@ bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, unsigned SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, + ArrayRef Cond, DebugLoc DL) const { assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 1 || Cond.size() == 0) && diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.h b/llvm/lib/Target/Sparc/SparcInstrInfo.h index 6e08418..15673f1 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.h +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.h @@ -73,8 +73,7 @@ public: unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, + MachineBasicBlock *FBB, ArrayRef Cond, DebugLoc DL) const override; void copyPhysReg(MachineBasicBlock &MBB, diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp index 4346850..5d4a34f 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -362,7 +362,7 @@ ReverseBranchCondition(SmallVectorImpl &Cond) const { unsigned SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, + ArrayRef Cond, DebugLoc DL) const { // In this function we output 32-bit branches, which should always // have enough range. They can be shortened and relaxed by later code @@ -530,8 +530,7 @@ isProfitableToIfCvt(MachineBasicBlock &TMBB, } bool SystemZInstrInfo:: -PredicateInstruction(MachineInstr *MI, - const SmallVectorImpl &Pred) const { +PredicateInstruction(MachineInstr *MI, ArrayRef Pred) const { assert(Pred.size() == 2 && "Invalid condition"); unsigned CCValid = Pred[0].getImm(); unsigned CCMask = Pred[1].getImm(); diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h index e47f2ee..31c9db2 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h @@ -149,8 +149,7 @@ public: bool AllowModify) const override; unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, + MachineBasicBlock *FBB, ArrayRef Cond, DebugLoc DL) const override; bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override; @@ -167,8 +166,7 @@ public: unsigned NumCyclesF, unsigned ExtraPredCyclesF, const BranchProbability &Probability) const override; bool PredicateInstruction(MachineInstr *MI, - const SmallVectorImpl &Pred) const - override; + ArrayRef Pred) const override; void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override; diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index c122996..cdaed77 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -3622,8 +3622,7 @@ unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { unsigned X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, + MachineBasicBlock *FBB, ArrayRef Cond, DebugLoc DL) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); @@ -3671,7 +3670,7 @@ X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, bool X86InstrInfo:: canInsertSelect(const MachineBasicBlock &MBB, - const SmallVectorImpl &Cond, + ArrayRef Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const { // Not all subtargets have cmov instructions. @@ -3708,8 +3707,7 @@ canInsertSelect(const MachineBasicBlock &MBB, void X86InstrInfo::insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, - unsigned DstReg, - const SmallVectorImpl &Cond, + unsigned DstReg, ArrayRef Cond, unsigned TrueReg, unsigned FalseReg) const { MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); assert(Cond.size() == 1 && "Invalid Cond array"); diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h index 9d0aef3..a716ca0 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.h +++ b/llvm/lib/Target/X86/X86InstrInfo.h @@ -269,16 +269,13 @@ public: bool AllowModify) const override; unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, + MachineBasicBlock *FBB, ArrayRef Cond, DebugLoc DL) const override; - bool canInsertSelect(const MachineBasicBlock&, - const SmallVectorImpl &Cond, + bool canInsertSelect(const MachineBasicBlock&, ArrayRef Cond, unsigned, unsigned, int&, int&, int&) const override; void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, - unsigned DstReg, - const SmallVectorImpl &Cond, + unsigned DstReg, ArrayRef Cond, unsigned TrueReg, unsigned FalseReg) const override; void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp index c310aa3..72058dd 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp @@ -281,7 +281,7 @@ XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, unsigned XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, + ArrayRef Cond, DebugLoc DL)const{ // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.h b/llvm/lib/Target/XCore/XCoreInstrInfo.h index 60bb3f8..b958c36 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.h +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.h @@ -56,8 +56,7 @@ public: bool AllowModify) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, + MachineBasicBlock *FBB, ArrayRef Cond, DebugLoc DL) const override; unsigned RemoveBranch(MachineBasicBlock &MBB) const override; -- 2.7.4