From c84722ff277a6848dfa17d137dcf21d64cdfb972 Mon Sep 17 00:00:00 2001 From: Oliver Cruickshank Date: Fri, 20 Sep 2019 15:03:44 +0000 Subject: [PATCH] [ARM] Fix CTTZ not generating correct instructions MVE CTTZ intrinsic should have been set to Custom, not Expand llvm-svn: 372401 --- llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 +- llvm/test/CodeGen/Thumb2/mve-cttz.ll | 42 ++++++++++----------------------- 2 files changed, 13 insertions(+), 31 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index e30b878..fbcdbbc 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -262,7 +262,7 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) { setOperationAction(ISD::MLOAD, VT, Custom); setOperationAction(ISD::MSTORE, VT, Legal); setOperationAction(ISD::CTLZ, VT, Legal); - setOperationAction(ISD::CTTZ, VT, Expand); + setOperationAction(ISD::CTTZ, VT, Custom); setOperationAction(ISD::BITREVERSE, VT, Legal); setOperationAction(ISD::BSWAP, VT, Legal); diff --git a/llvm/test/CodeGen/Thumb2/mve-cttz.ll b/llvm/test/CodeGen/Thumb2/mve-cttz.ll index c30906f..d1034fb 100644 --- a/llvm/test/CodeGen/Thumb2/mve-cttz.ll +++ b/llvm/test/CodeGen/Thumb2/mve-cttz.ll @@ -44,12 +44,9 @@ entry: define arm_aapcs_vfpcc <4 x i32> @cttz_4i32_0_t(<4 x i32> %src){ ; CHECK-LABEL: cttz_4i32_0_t: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i32 q1, #0x1 -; CHECK-NEXT: vsub.i32 q1, q0, q1 -; CHECK-NEXT: vbic q0, q1, q0 -; CHECK-NEXT: vmov.i32 q1, #0x20 +; CHECK-NEXT: movs r0, #32 +; CHECK-NEXT: vbrsr.32 q0, q0, r0 ; CHECK-NEXT: vclz.i32 q0, q0 -; CHECK-NEXT: vsub.i32 q0, q1, q0 ; CHECK-NEXT: bx lr entry: %0 = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %src, i1 0) @@ -59,12 +56,9 @@ entry: define arm_aapcs_vfpcc <8 x i16> @cttz_8i16_0_t(<8 x i16> %src){ ; CHECK-LABEL: cttz_8i16_0_t: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i16 q1, #0x1 -; CHECK-NEXT: vsub.i16 q1, q0, q1 -; CHECK-NEXT: vbic q0, q1, q0 -; CHECK-NEXT: vmov.i16 q1, #0x10 +; CHECK-NEXT: movs r0, #16 +; CHECK-NEXT: vbrsr.16 q0, q0, r0 ; CHECK-NEXT: vclz.i16 q0, q0 -; CHECK-NEXT: vsub.i16 q0, q1, q0 ; CHECK-NEXT: bx lr entry: %0 = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %src, i1 0) @@ -74,12 +68,9 @@ entry: define arm_aapcs_vfpcc <16 x i8> @cttz_16i8_0_t(<16 x i8> %src) { ; CHECK-LABEL: cttz_16i8_0_t: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i8 q1, #0x1 -; CHECK-NEXT: vsub.i8 q1, q0, q1 -; CHECK-NEXT: vbic q0, q1, q0 -; CHECK-NEXT: vmov.i8 q1, #0x8 +; CHECK-NEXT: movs r0, #8 +; CHECK-NEXT: vbrsr.8 q0, q0, r0 ; CHECK-NEXT: vclz.i8 q0, q0 -; CHECK-NEXT: vsub.i8 q0, q1, q0 ; CHECK-NEXT: bx lr entry: %0 = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %src, i1 0) @@ -129,12 +120,9 @@ entry: define arm_aapcs_vfpcc <4 x i32> @cttz_4i32_1_t(<4 x i32> %src){ ; CHECK-LABEL: cttz_4i32_1_t: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i32 q1, #0x1 -; CHECK-NEXT: vsub.i32 q1, q0, q1 -; CHECK-NEXT: vbic q0, q1, q0 -; CHECK-NEXT: vmov.i32 q1, #0x20 +; CHECK-NEXT: movs r0, #32 +; CHECK-NEXT: vbrsr.32 q0, q0, r0 ; CHECK-NEXT: vclz.i32 q0, q0 -; CHECK-NEXT: vsub.i32 q0, q1, q0 ; CHECK-NEXT: bx lr entry: %0 = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %src, i1 1) @@ -144,12 +132,9 @@ entry: define arm_aapcs_vfpcc <8 x i16> @cttz_8i16_1_t(<8 x i16> %src){ ; CHECK-LABEL: cttz_8i16_1_t: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i16 q1, #0x1 -; CHECK-NEXT: vsub.i16 q1, q0, q1 -; CHECK-NEXT: vbic q0, q1, q0 -; CHECK-NEXT: vmov.i16 q1, #0x10 +; CHECK-NEXT: movs r0, #16 +; CHECK-NEXT: vbrsr.16 q0, q0, r0 ; CHECK-NEXT: vclz.i16 q0, q0 -; CHECK-NEXT: vsub.i16 q0, q1, q0 ; CHECK-NEXT: bx lr entry: %0 = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %src, i1 1) @@ -159,12 +144,9 @@ entry: define arm_aapcs_vfpcc <16 x i8> @cttz_16i8_1_t(<16 x i8> %src) { ; CHECK-LABEL: cttz_16i8_1_t: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i8 q1, #0x1 -; CHECK-NEXT: vsub.i8 q1, q0, q1 -; CHECK-NEXT: vbic q0, q1, q0 -; CHECK-NEXT: vmov.i8 q1, #0x8 +; CHECK-NEXT: movs r0, #8 +; CHECK-NEXT: vbrsr.8 q0, q0, r0 ; CHECK-NEXT: vclz.i8 q0, q0 -; CHECK-NEXT: vsub.i8 q0, q1, q0 ; CHECK-NEXT: bx lr entry: %0 = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %src, i1 1) -- 2.7.4