From c80137fcba00be5217c37ad65e398e51cd4bdebc Mon Sep 17 00:00:00 2001 From: =?utf8?q?Daniel=20Sch=C3=BCrmann?= Date: Tue, 25 Oct 2022 09:44:43 +0200 Subject: [PATCH] radv/rt: overwrite hit args with undef in case of a miss This helps some variable coalescing. Part-of: --- src/amd/vulkan/radv_pipeline_rt.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/amd/vulkan/radv_pipeline_rt.c b/src/amd/vulkan/radv_pipeline_rt.c index 5f25c7e..3006d24 100644 --- a/src/amd/vulkan/radv_pipeline_rt.c +++ b/src/amd/vulkan/radv_pipeline_rt.c @@ -712,6 +712,11 @@ lower_rt_instructions(nir_shader *shader, struct rt_variables *vars, unsigned ca } case nir_intrinsic_execute_miss_amd: { nir_store_var(&b_shader, vars->tmax, intr->src[0].ssa, 0x1); + nir_ssa_def *undef = nir_ssa_undef(&b_shader, 1, 32); + nir_store_var(&b_shader, vars->primitive_id, undef, 0x1); + nir_store_var(&b_shader, vars->instance_addr, nir_ssa_undef(&b_shader, 1, 64), 0x1); + nir_store_var(&b_shader, vars->geometry_id_and_flags, undef, 0x1); + nir_store_var(&b_shader, vars->hit_kind, undef, 0x1); nir_ssa_def *miss_index = nir_load_var(&b_shader, vars->miss_index); load_sbt_entry(&b_shader, vars, miss_index, SBT_MISS, 0); break; -- 2.7.4