From c7ed9679f97da003e8d2979090c00da2debf713d Mon Sep 17 00:00:00 2001 From: =?utf8?q?Tomasz=20Sowi=C5=84ski?= Date: Tue, 24 Oct 2023 15:34:38 +0200 Subject: [PATCH] [RISC-V] Disable not-yet-implemented EnC assertion (#93864) Proper EnC support for RISC-V would require development similar to #69679, for now disable the section. --- src/coreclr/jit/codegenriscv64.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/coreclr/jit/codegenriscv64.cpp b/src/coreclr/jit/codegenriscv64.cpp index 2f5c851..d45fd37 100644 --- a/src/coreclr/jit/codegenriscv64.cpp +++ b/src/coreclr/jit/codegenriscv64.cpp @@ -6908,10 +6908,12 @@ void CodeGen::genCreateAndStoreGCInfo(unsigned codeSize, // Now we can actually use those slot ID's to declare live ranges. gcInfo.gcMakeRegPtrTable(gcInfoEncoder, codeSize, prologSize, GCInfo::MAKE_REG_PTR_MODE_DO_WORK, &callCnt); +#ifdef FEATURE_REMAP_FUNCTION if (compiler->opts.compDbgEnC) { NYI_RISCV64("compDbgEnc in genCreateAndStoreGCInfo-----unimplemented/unused on RISCV64 yet----"); } +#endif // FEATURE_REMAP_FUNCTION if (compiler->opts.IsReversePInvoke()) { -- 2.7.4