From c7dd7f20b099d98c1941240e5c8586290dd53182 Mon Sep 17 00:00:00 2001
From: Peter Rong <PeterRong96@gmail.com>
Date: Wed, 12 Oct 2022 11:26:57 -0700
Subject: [PATCH] [PowerPC] Pre-commit unit test change for D132978

---
 .../CodeGen/PowerPC/variable_elem_vec_extracts.ll  | 198 ++++++++++++---------
 1 file changed, 117 insertions(+), 81 deletions(-)

diff --git a/llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll b/llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll
index b149c74..9c685ed 100644
--- a/llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll
+++ b/llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -ppc-late-peephole=true < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
 ; RUN:  --check-prefix=CHECK-BE
@@ -6,109 +7,144 @@
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @geti(<4 x i32> %a, i32 signext %b) {
+; CHECK-LABEL: geti:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li 3, 2
+; CHECK-NEXT:    andc 3, 3, 5
+; CHECK-NEXT:    sldi 3, 3, 2
+; CHECK-NEXT:    lvsl 3, 0, 3
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    and 3, 3, 5
+; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    sldi 3, 3, 5
+; CHECK-NEXT:    mfvsrd 4, 34
+; CHECK-NEXT:    srd 3, 4, 3
+; CHECK-NEXT:    extsw 3, 3
+; CHECK-NEXT:    blr
+;
+; CHECK-BE-LABEL: geti:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    andi. 4, 5, 2
+; CHECK-BE-NEXT:    li 3, 1
+; CHECK-BE-NEXT:    sldi 4, 4, 2
+; CHECK-BE-NEXT:    andc 3, 3, 5
+; CHECK-BE-NEXT:    lvsl 3, 0, 4
+; CHECK-BE-NEXT:    sldi 3, 3, 5
+; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    mfvsrd 4, 34
+; CHECK-BE-NEXT:    srd 3, 4, 3
+; CHECK-BE-NEXT:    extsw 3, 3
+; CHECK-BE-NEXT:    blr
+;
+; CHECK-P7-LABEL: geti:
+; CHECK-P7:       # %bb.0: # %entry
+; CHECK-P7-NEXT:    addi 3, 1, -16
+; CHECK-P7-NEXT:    rlwinm 4, 5, 2, 28, 29
+; CHECK-P7-NEXT:    stxvw4x 34, 0, 3
+; CHECK-P7-NEXT:    lwax 3, 3, 4
+; CHECK-P7-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %a, i32 %b
   ret i32 %vecext
-; CHECK-LABEL: @geti
-; CHECK-P7-LABEL: @geti
-; CHECK-BE-LABEL: @geti
-; CHECK-DAG: li [[TRUNCREG:[0-9]+]], 2
-; CHECK-DAG: andc [[MASKREG:[0-9]+]], [[TRUNCREG]], 5
-; CHECK-DAG: sldi [[SHIFTREG:[0-9]+]], [[MASKREG]], 2
-; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]]
-; CHECK-DAG: vperm [[PERMVEC:[0-9]+]], 2, 2, [[SHMSKREG]]
-; CHECK-DAG: li [[ONEREG:[0-9]+]], 1
-; CHECK-DAG: and [[ELEMSREG:[0-9]+]], [[ONEREG]], 5
-; CHECK-DAG: sldi [[SHAMREG:[0-9]+]], [[ELEMSREG]], 5
-; CHECK: mfvsrd [[TOGPR:[0-9]+]],
-; CHECK: srd [[RSHREG:[0-9]+]], [[TOGPR]], [[SHAMREG]]
-; CHECK: extsw 3, [[RSHREG]]
-; CHECK-P7-DAG: rlwinm [[ELEMOFFREG:[0-9]+]], 5, 2, 28, 29
-; CHECK-P7-DAG: stxvw4x 34,
-; CHECK-P7: lwax 3, 3, [[ELEMOFFREG]]
-; CHECK-BE-DAG: andi. [[ANDREG:[0-9]+]], 5, 2
-; CHECK-BE-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 2
-; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
-; CHECK-BE-DAG: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]]
-; CHECK-BE-DAG: li [[IMMREG:[0-9]+]], 1
-; CHECK-BE-DAG: andc [[ANDCREG:[0-9]+]], [[IMMREG]], 5
-; CHECK-BE-DAG: sldi [[SHAMREG:[0-9]+]], [[ANDCREG]], 5
-; CHECK-BE: mfvsrd [[TOGPR:[0-9]+]],
-; CHECK-BE: srd [[RSHREG:[0-9]+]], [[TOGPR]], [[SHAMREG]]
-; CHECK-BE: extsw 3, [[RSHREG]]
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @getl(<2 x i64> %a, i32 signext %b) {
+; CHECK-LABEL: getl:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    andc 3, 3, 5
+; CHECK-NEXT:    sldi 3, 3, 3
+; CHECK-NEXT:    lvsl 3, 0, 3
+; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    mfvsrd 3, 34
+; CHECK-NEXT:    blr
+;
+; CHECK-BE-LABEL: getl:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    andi. 3, 5, 1
+; CHECK-BE-NEXT:    sldi 3, 3, 3
+; CHECK-BE-NEXT:    lvsl 3, 0, 3
+; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    mfvsrd 3, 34
+; CHECK-BE-NEXT:    blr
+;
+; CHECK-P7-LABEL: getl:
+; CHECK-P7:       # %bb.0: # %entry
+; CHECK-P7-NEXT:    addi 3, 1, -16
+; CHECK-P7-NEXT:    rlwinm 4, 5, 3, 28, 28
+; CHECK-P7-NEXT:    stxvd2x 34, 0, 3
+; CHECK-P7-NEXT:    ldx 3, 3, 4
+; CHECK-P7-NEXT:    blr
 entry:
   %vecext = extractelement <2 x i64> %a, i32 %b
   ret i64 %vecext
-; CHECK-LABEL: @getl
-; CHECK-P7-LABEL: @getl
-; CHECK-BE-LABEL: @getl
-; CHECK-DAG: li [[TRUNCREG:[0-9]+]], 1
-; CHECK-DAG: andc [[MASKREG:[0-9]+]], [[TRUNCREG]], 5
-; CHECK-DAG: sldi [[SHIFTREG:[0-9]+]], [[MASKREG]], 3
-; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]]
-; CHECK-DAG: vperm [[PERMVEC:[0-9]+]], 2, 2, [[SHMSKREG]]
-; CHECK: mfvsrd 3,
-; CHECK-P7-DAG: rlwinm [[ELEMOFFREG:[0-9]+]], 5, 3, 28, 28
-; CHECK-P7-DAG: stxvd2x 34,
-; CHECK-P7: ldx 3, 3, [[ELEMOFFREG]]
-; CHECK-BE-DAG: andi. [[ANDREG:[0-9]+]], 5, 1
-; CHECK-BE-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 3
-; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
-; CHECK-BE-DAG: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]]
-; CHECK-BE: mfvsrd 3,
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @getf(<4 x float> %a, i32 signext %b) {
+; CHECK-LABEL: getf:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xori 3, 5, 3
+; CHECK-NEXT:    sldi 3, 3, 2
+; CHECK-NEXT:    lvsl 3, 0, 3
+; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    xscvspdpn 1, 34
+; CHECK-NEXT:    blr
+;
+; CHECK-BE-LABEL: getf:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    sldi 3, 5, 2
+; CHECK-BE-NEXT:    lvsl 3, 0, 3
+; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    xscvspdpn 1, 34
+; CHECK-BE-NEXT:    blr
+;
+; CHECK-P7-LABEL: getf:
+; CHECK-P7:       # %bb.0: # %entry
+; CHECK-P7-NEXT:    addi 3, 1, -16
+; CHECK-P7-NEXT:    rlwinm 4, 5, 2, 28, 29
+; CHECK-P7-NEXT:    stxvw4x 34, 0, 3
+; CHECK-P7-NEXT:    lfsx 1, 3, 4
+; CHECK-P7-NEXT:    blr
 entry:
   %vecext = extractelement <4 x float> %a, i32 %b
   ret float %vecext
-; CHECK-LABEL: @getf
-; CHECK-P7-LABEL: @getf
-; CHECK-BE-LABEL: @getf
-; CHECK: xori [[TRUNCREG:[0-9]+]], 5, 3
-; CHECK: sldi [[SHIFTREG:[0-9]+]], [[TRUNCREG]], 2
-; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]]
-; CHECK: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]]
-; CHECK: xscvspdpn 1,
-; CHECK-P7-DAG: rlwinm [[ELEMOFFREG:[0-9]+]], 5, 2, 28, 29
-; CHECK-P7-DAG: stxvw4x 34,
-; CHECK-P7: lfsx 1, 3, [[ELEMOFFREG]]
-; CHECK-BE: sldi [[ELNOREG:[0-9]+]], 5, 2
-; CHECK-BE: lvsl [[SHMSKREG:[0-9]+]], 0, [[ELNOREG]]
-; CHECK-BE: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]]
-; CHECK-BE: xscvspdpn 1,
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @getd(<2 x double> %a, i32 signext %b) {
+; CHECK-LABEL: getd:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    andc 3, 3, 5
+; CHECK-NEXT:    sldi 3, 3, 3
+; CHECK-NEXT:    lvsl 3, 0, 3
+; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    xxlor 1, 34, 34
+; CHECK-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
+; CHECK-NEXT:    blr
+;
+; CHECK-BE-LABEL: getd:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    andi. 3, 5, 1
+; CHECK-BE-NEXT:    sldi 3, 3, 3
+; CHECK-BE-NEXT:    lvsl 3, 0, 3
+; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    xxlor 1, 34, 34
+; CHECK-BE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
+; CHECK-BE-NEXT:    blr
+;
+; CHECK-P7-LABEL: getd:
+; CHECK-P7:       # %bb.0: # %entry
+; CHECK-P7-NEXT:    andi. 3, 5, 1
+; CHECK-P7-NEXT:    sldi 3, 3, 3
+; CHECK-P7-NEXT:    lvsl 3, 0, 3
+; CHECK-P7-NEXT:    vperm 2, 2, 2, 3
+; CHECK-P7-NEXT:    xxlor 1, 34, 34
+; CHECK-P7-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
+; CHECK-P7-NEXT:    blr
 entry:
   %vecext = extractelement <2 x double> %a, i32 %b
   ret double %vecext
-; CHECK-LABEL: @getd
-; CHECK-P7-LABEL: @getd
-; CHECK-BE-LABEL: @getd
-; CHECK: li [[TRUNCREG:[0-9]+]], 1
-; CHECK: andc [[MASKREG:[0-9]+]], [[TRUNCREG]], 5
-; CHECK: sldi [[SHIFTREG:[0-9]+]], [[MASKREG]], 3
-; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]]
-; CHECK: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]]
-; FIXME: the instruction below is a redundant regclass copy, to be removed
-; CHECK: xxlor 1,
-; CHECK-P7-DAG: andi. [[ANDREG:[0-9]+]], 5, 1
-; CHECK-P7-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 3
-; CHECK-P7-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
-; CHECK-P7-DAG: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]]
-; FIXME: the instruction below is a redundant regclass copy, to be removed
-; CHECK-P7: xxlor 1,
-; CHECK-BE-DAG: andi. [[ANDREG:[0-9]+]], 5, 1
-; CHECK-BE-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 3
-; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
-; CHECK-BE-DAG: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]]
-; FIXME: the instruction below is a redundant regclass copy, to be removed
-; CHECK-BE: xxlor 1,
 }
-- 
2.7.4