From c7d8f2df92f65ed467e1f1a6baf97e034f35bf58 Mon Sep 17 00:00:00 2001 From: Kaifu Hu Date: Thu, 10 Jan 2019 15:14:49 +0800 Subject: [PATCH] hdmi: support 1440x2560p60hz modes [1/1] PD#IPTV-1032 Problem: Need support 1440x2560p60hz Solution: Porting VESA code and 1440x2560p60hz Verify: g12b/w400 Change-Id: I3cf38bebc29b76aed50fe2ced7b47e27f2d1af06 Signed-off-by: Kaifu Hu --- .../vout/hdmitx/hdmi_common/hdmi_parameters.c | 1248 +++++++++++++++++++- .../media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c | 288 ++++- .../media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c | 59 + .../media/vout/hdmitx/hdmi_tx_20/hdmi_tx_video.c | 326 +++++ .../media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c | 807 +++++++++++++ .../media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c | 193 ++- .../media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c | 78 ++ .../media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c | 18 +- .../media/vout/hdmitx/hdmi_tx_20/hw/hw_gxl.c | 240 ++++ .../linux/amlogic/media/vout/hdmi_tx/hdmi_common.h | 43 + .../amlogic/media/vout/hdmi_tx/hdmi_tx_module.h | 2 + 11 files changed, 3263 insertions(+), 39 deletions(-) diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c b/drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c index 89a3ce1..cf5e192 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c @@ -1385,7 +1385,1204 @@ static struct hdmi_format_para fmt_para_null_hdmi_fmt = { }, }; -/* end of Y420 modes*/ +static struct hdmi_format_para fmt_para_2560x1080p50_64x27 = { + .vic = HDMI_2560x1080p50_64x27, + .name = "2560x1080p50hz", + .sname = "2560x1080p50hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 185625, + .timing = { + .pixel_freq = 185625, + .h_freq = 56250, + .v_freq = 50000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 2560, + .h_total = 3300, + .h_blank = 740, + .h_front = 548, + .h_sync = 44, + .h_back = 148, + .v_active = 1080, + .v_total = 1125, + .v_blank = 45, + .v_front = 4, + .v_sync = 5, + .v_back = 36, + .v_sync_ln = 1, + }, + .hdmitx_vinfo = { + .name = "2560x1080p50hz", + .mode = VMODE_HDMI, + .width = 2560, + .height = 1080, + .field_height = 1080, + .aspect_ratio_num = 64, + .aspect_ratio_den = 27, + .sync_duration_num = 50, + .sync_duration_den = 1, + .video_clk = 185625000, + .htotal = 3300, + .vtotal = 1125, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; + +static struct hdmi_format_para fmt_para_2560x1080p60_64x27 = { + .vic = HDMI_2560x1080p60_64x27, + .name = "2560x1080p60hz", + .sname = "2560x1080p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 198000, + .timing = { + .pixel_freq = 198000, + .h_freq = 66000, + .v_freq = 60000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 2560, + .h_total = 3000, + .h_blank = 440, + .h_front = 248, + .h_sync = 44, + .h_back = 148, + .v_active = 1080, + .v_total = 1100, + .v_blank = 20, + .v_front = 4, + .v_sync = 5, + .v_back = 11, + .v_sync_ln = 1, + }, + .hdmitx_vinfo = { + .name = "2560x1080p60hz", + .mode = VMODE_HDMI, + .width = 2560, + .height = 1080, + .field_height = 1080, + .aspect_ratio_num = 64, + .aspect_ratio_den = 27, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 198000000, + .htotal = 3000, + .vtotal = 1100, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; + +/* + * VESA timing describe + */ +static struct hdmi_format_para fmt_para_vesa_640x480p60_4x3 = { + .vic = HDMIV_640x480p60hz, + .name = "640x480p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 25175, + .timing = { + .pixel_freq = 25175, + .h_freq = 26218, + .v_freq = 59940, + .vsync = 60, + .vsync_polarity = 0, + .hsync_polarity = 0, + .h_active = 640, + .h_total = 800, + .h_blank = 160, + .h_front = 16, + .h_sync = 96, + .h_back = 48, + .v_active = 480, + .v_total = 525, + .v_blank = 45, + .v_front = 10, + .v_sync = 2, + .v_back = 33, + .v_sync_ln = 1, + }, + .hdmitx_vinfo = { + .name = "640x480p60hz", + .mode = VMODE_HDMI, + .width = 640, + .height = 480, + .field_height = 480, + .aspect_ratio_num = 4, + .aspect_ratio_den = 3, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 25175000, + .htotal = 800, + .vtotal = 525, + .fr_adj_type = VOUT_FR_ADJ_HDMI, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_800x480p60_4x3 = { + .vic = HDMIV_800x480p60hz, + .name = "800x480p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 29760, + .timing = { + .pixel_freq = 29760, + .h_freq = 30000, + .v_freq = 60000, + .vsync = 60, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 800, + .h_total = 992, + .h_blank = 192, + .h_front = 24, + .h_sync = 72, + .h_back = 96, + .v_active = 480, + .v_total = 500, + .v_blank = 20, + .v_front = 3, + .v_sync = 7, + .v_back = 10, + .v_sync_ln = 1, + }, + .hdmitx_vinfo = { + .name = "800x480p60hz", + .mode = VMODE_HDMI, + .width = 800, + .height = 480, + .field_height = 480, + .aspect_ratio_num = 4, + .aspect_ratio_den = 3, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 29760000, + .htotal = 992, + .vtotal = 500, + .fr_adj_type = VOUT_FR_ADJ_HDMI, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_800x600p60_4x3 = { + .vic = HDMIV_800x600p60hz, + .name = "800x600p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 40000, + .timing = { + .pixel_freq = 66666, + .h_freq = 37879, + .v_freq = 60317, + .vsync = 60, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 800, + .h_total = 1056, + .h_blank = 256, + .h_front = 40, + .h_sync = 128, + .h_back = 88, + .v_active = 600, + .v_total = 628, + .v_blank = 28, + .v_front = 1, + .v_sync = 4, + .v_back = 23, + .v_sync_ln = 1, + }, + .hdmitx_vinfo = { + .name = "800x600p60hz", + .mode = VMODE_HDMI, + .width = 800, + .height = 600, + .field_height = 600, + .aspect_ratio_num = 4, + .aspect_ratio_den = 3, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 66666000, + .htotal = 1056, + .vtotal = 628, + .fr_adj_type = VOUT_FR_ADJ_HDMI, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_852x480p60_213x120 = { + .vic = HDMIV_852x480p60hz, + .name = "852x480p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 30240, + .timing = { + .pixel_freq = 30240, + .h_freq = 31900, + .v_freq = 59960, + .vsync = 60, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 852, + .h_total = 948, + .h_blank = 96, + .h_front = 40, + .h_sync = 16, + .h_back = 40, + .v_active = 480, + .v_total = 532, + .v_blank = 52, + .v_front = 10, + .v_sync = 2, + .v_back = 40, + .v_sync_ln = 1, + }, + .hdmitx_vinfo = { + .name = "852x480p60hz", + .mode = VMODE_HDMI, + .width = 852, + .height = 480, + .field_height = 480, + .aspect_ratio_num = 213, + .aspect_ratio_den = 120, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 30240000, + .htotal = 948, + .vtotal = 532, + .fr_adj_type = VOUT_FR_ADJ_HDMI, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_854x480p60_427x240 = { + .vic = HDMIV_854x480p60hz, + .name = "854x480p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 30240, + .timing = { + .pixel_freq = 30240, + .h_freq = 31830, + .v_freq = 59950, + .vsync = 60, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 854, + .h_total = 950, + .h_blank = 96, + .h_front = 40, + .h_sync = 16, + .h_back = 40, + .v_active = 480, + .v_total = 531, + .v_blank = 51, + .v_front = 10, + .v_sync = 2, + .v_back = 39, + .v_sync_ln = 1, + }, + .hdmitx_vinfo = { + .name = "854x480p60hz", + .mode = VMODE_HDMI, + .width = 854, + .height = 480, + .field_height = 480, + .aspect_ratio_num = 427, + .aspect_ratio_den = 240, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 30240000, + .htotal = 950, + .vtotal = 531, + .fr_adj_type = VOUT_FR_ADJ_HDMI, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1024x600p60_17x10 = { + .vic = HDMIV_1024x600p60hz, + .name = "1024x600p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 50400, + .timing = { + .pixel_freq = 50400, + .h_freq = 38280, + .v_freq = 60000, + .vsync = 60, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1024, + .h_total = 1344, + .h_blank = 320, + .h_front = 24, + .h_sync = 136, + .h_back = 160, + .v_active = 600, + .v_total = 638, + .v_blank = 38, + .v_front = 3, + .v_sync = 6, + .v_back = 29, + .v_sync_ln = 1, + }, + .hdmitx_vinfo = { + .name = "1024x600p60hz", + .mode = VMODE_HDMI, + .width = 1024, + .height = 600, + .field_height = 600, + .aspect_ratio_num = 17, + .aspect_ratio_den = 10, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 50400000, + .htotal = 1344, + .vtotal = 638, + .fr_adj_type = VOUT_FR_ADJ_HDMI, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1024x768p60_4x3 = { + .vic = HDMIV_1024x768p60hz, + .name = "1024x768p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 79500, + .timing = { + .pixel_freq = 79500, + .h_freq = 48360, + .v_freq = 60004, + .vsync = 60, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1024, + .h_total = 1344, + .h_blank = 320, + .h_front = 24, + .h_sync = 136, + .h_back = 160, + .v_active = 768, + .v_total = 806, + .v_blank = 38, + .v_front = 3, + .v_sync = 6, + .v_back = 29, + .v_sync_ln = 1, + }, + .hdmitx_vinfo = { + .name = "1024x768p60hz", + .mode = VMODE_HDMI, + .width = 1024, + .height = 768, + .field_height = 768, + .aspect_ratio_num = 4, + .aspect_ratio_den = 3, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 79500000, + .htotal = 1344, + .vtotal = 806, + .fr_adj_type = VOUT_FR_ADJ_HDMI, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1152x864p75_4x3 = { + .vic = HDMIV_1152x864p75hz, + .name = "1152x864p75hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 108000, + .timing = { + .pixel_freq = 108000, + .h_freq = 67500, + .v_freq = 75000, + .vsync = 75, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1152, + .h_total = 1600, + .h_blank = 448, + .h_front = 64, + .h_sync = 128, + .h_back = 256, + .v_active = 864, + .v_total = 900, + .v_blank = 36, + .v_front = 1, + .v_sync = 3, + .v_back = 32, + }, + .hdmitx_vinfo = { + .name = "1152x864p75hz", + .mode = VMODE_HDMI, + .width = 1152, + .height = 864, + .field_height = 864, + .aspect_ratio_num = 4, + .aspect_ratio_den = 3, + .sync_duration_num = 75, + .sync_duration_den = 1, + .video_clk = 108000000, + .htotal = 1600, + .vtotal = 900, + .fr_adj_type = VOUT_FR_ADJ_HDMI, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1280x768p60_5x3 = { + .vic = HDMIV_1280x768p60hz, + .name = "1280x768p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 79500, + .timing = { + .pixel_freq = 79500, + .h_freq = 47776, + .v_freq = 59870, + .vsync = 60, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1280, + .h_total = 1664, + .h_blank = 384, + .h_front = 64, + .h_sync = 128, + .h_back = 192, + .v_active = 768, + .v_total = 798, + .v_blank = 30, + .v_front = 3, + .v_sync = 7, + .v_back = 20, + }, + .hdmitx_vinfo = { + .name = "1280x768p60hz", + .mode = VMODE_HDMI, + .width = 1280, + .height = 768, + .field_height = 768, + .aspect_ratio_num = 5, + .aspect_ratio_den = 3, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 79500000, + .htotal = 1664, + .vtotal = 798, + .fr_adj_type = VOUT_FR_ADJ_HDMI, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1280x800p60_8x5 = { + .vic = HDMIV_1280x800p60hz, + .name = "1280x800p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 83500, + .timing = { + .pixel_freq = 83500, + .h_freq = 49380, + .v_freq = 59910, + .vsync = 60, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1280, + .h_total = 1440, + .h_blank = 160, + .h_front = 48, + .h_sync = 32, + .h_back = 80, + .v_active = 800, + .v_total = 823, + .v_blank = 23, + .v_front = 3, + .v_sync = 6, + .v_back = 14, + .v_sync_ln = 1, + }, + .hdmitx_vinfo = { + .name = "1280x800p60hz", + .mode = VMODE_HDMI, + .width = 1280, + .height = 800, + .field_height = 800, + .aspect_ratio_num = 8, + .aspect_ratio_den = 5, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 83500000, + .htotal = 1440, + .vtotal = 823, + .fr_adj_type = VOUT_FR_ADJ_HDMI, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1280x960p60_4x3 = { + .vic = HDMIV_1280x960p60hz, + .name = "1280x960p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 108000, + .timing = { + .pixel_freq = 108000, + .h_freq = 60000, + .v_freq = 60000, + .vsync = 60, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1280, + .h_total = 1800, + .h_blank = 520, + .h_front = 96, + .h_sync = 112, + .h_back = 312, + .v_active = 960, + .v_total = 1000, + .v_blank = 40, + .v_front = 1, + .v_sync = 3, + .v_back = 36, + }, + .hdmitx_vinfo = { + .name = "1280x960p60hz", + .mode = VMODE_HDMI, + .width = 1280, + .height = 960, + .field_height = 960, + .aspect_ratio_num = 4, + .aspect_ratio_den = 3, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 108000000, + .htotal = 1800, + .vtotal = 1000, + .fr_adj_type = VOUT_FR_ADJ_HDMI, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1280x1024p60_5x4 = { + .vic = HDMIV_1280x1024p60hz, + .name = "1280x1024p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 108000, + .timing = { + .pixel_freq = 108000, + .h_freq = 64080, + .v_freq = 60020, + .vsync = 60, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1280, + .h_total = 1688, + .h_blank = 408, + .h_front = 48, + .h_sync = 112, + .h_back = 248, + .v_active = 1024, + .v_total = 1066, + .v_blank = 42, + .v_front = 1, + .v_sync = 3, + .v_back = 38, + .v_sync_ln = 1, + }, + .hdmitx_vinfo = { + .name = "1280x1024p60hz", + .mode = VMODE_HDMI, + .width = 1280, + .height = 1024, + .field_height = 1024, + .aspect_ratio_num = 5, + .aspect_ratio_den = 4, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 108000000, + .htotal = 1688, + .vtotal = 1066, + .fr_adj_type = VOUT_FR_ADJ_HDMI, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1360x768p60_16x9 = { + .vic = HDMIV_1360x768p60hz, + .name = "1360x768p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 855000, + .timing = { + .pixel_freq = 855000, + .h_freq = 47700, + .v_freq = 60015, + .vsync = 60, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1360, + .h_total = 1792, + .h_blank = 432, + .h_front = 64, + .h_sync = 112, + .h_back = 256, + .v_active = 768, + .v_total = 795, + .v_blank = 27, + .v_front = 3, + .v_sync = 6, + .v_back = 18, + .v_sync_ln = 1, + }, + .hdmitx_vinfo = { + .name = "1360x768p60hz", + .mode = VMODE_HDMI, + .width = 1360, + .height = 768, + .field_height = 768, + .aspect_ratio_num = 16, + .aspect_ratio_den = 9, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 85500000, + .htotal = 1792, + .vtotal = 795, + .fr_adj_type = VOUT_FR_ADJ_HDMI, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1366x768p60_16x9 = { + .vic = HDMIV_1366x768p60hz, + .name = "1366x768p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 85500, + .timing = { + .pixel_freq = 85500, + .h_freq = 47880, + .v_freq = 59790, + .vsync = 60, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1366, + .h_total = 1792, + .h_blank = 426, + .h_front = 70, + .h_sync = 143, + .h_back = 213, + .v_active = 768, + .v_total = 798, + .v_blank = 30, + .v_front = 3, + .v_sync = 3, + .v_back = 24, + .v_sync_ln = 1, + }, + .hdmitx_vinfo = { + .name = "1366x768p60hz", + .mode = VMODE_HDMI, + .width = 1366, + .height = 768, + .field_height = 768, + .aspect_ratio_num = 16, + .aspect_ratio_den = 9, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 85500000, + .htotal = 1792, + .vtotal = 798, + .fr_adj_type = VOUT_FR_ADJ_HDMI, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1400x1050p60_4x3 = { + .vic = HDMIV_1400x1050p60hz, + .name = "1400x1050p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 121750, + .timing = { + .pixel_freq = 121750, + .h_freq = 65317, + .v_freq = 59978, + .vsync = 60, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1400, + .h_total = 1864, + .h_blank = 464, + .h_front = 88, + .h_sync = 144, + .h_back = 232, + .v_active = 1050, + .v_total = 1089, + .v_blank = 39, + .v_front = 3, + .v_sync = 4, + .v_back = 32, + .v_sync_ln = 1, + }, + .hdmitx_vinfo = { + .name = "1400x1050p60hz", + .mode = VMODE_HDMI, + .width = 1400, + .height = 1050, + .field_height = 1050, + .aspect_ratio_num = 4, + .aspect_ratio_den = 3, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 121750000, + .htotal = 1864, + .vtotal = 1089, + .fr_adj_type = VOUT_FR_ADJ_HDMI, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1440x900p60_8x5 = { + .vic = HDMIV_1440x900p60hz, + .name = "1440x900p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 106500, + .timing = { + .pixel_freq = 106500, + .h_freq = 56040, + .v_freq = 59887, + .vsync = 60, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1440, + .h_total = 1904, + .h_blank = 464, + .h_front = 80, + .h_sync = 152, + .h_back = 232, + .v_active = 900, + .v_total = 934, + .v_blank = 34, + .v_front = 3, + .v_sync = 6, + .v_back = 25, + .v_sync_ln = 1, + }, + .hdmitx_vinfo = { + .name = "1440x900p60hz", + .mode = VMODE_HDMI, + .width = 1440, + .height = 900, + .field_height = 900, + .aspect_ratio_num = 8, + .aspect_ratio_den = 5, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 106500000, + .htotal = 1904, + .vtotal = 934, + .fr_adj_type = VOUT_FR_ADJ_HDMI, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1440x2560p60_9x16 = { + .vic = HDMIV_1440x2560p60hz, + .name = "1440x2560p60hz", + .sname = "1440x2560p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 244850, + .timing = { + .pixel_freq = 244850, + .h_freq = 155760, + .v_freq = 59999, + .vsync = 60, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1440, + .h_total = 1572, + .h_blank = 132, + .h_front = 64, + .h_sync = 4, + .h_back = 64, + .v_active = 2560, + .v_total = 2596, + .v_blank = 36, + .v_front = 16, + .v_sync = 4, + .v_back = 16, + .v_sync_ln = 1, + }, + .hdmitx_vinfo = { + .name = "1440x2560p60hz", + .mode = VMODE_HDMI, + .width = 1440, + .height = 2560, + .field_height = 2560, + .aspect_ratio_num = 16, + .aspect_ratio_den = 9, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 244850000, + .htotal = 1572, + .vtotal = 2596, + .fr_adj_type = VOUT_FR_ADJ_HDMI, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1600x900p60_16x9 = { + .vic = HDMIV_1600x900p60hz, + .name = "1600x900p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 108000, + .timing = { + .pixel_freq = 108000, + .h_freq = 60000, + .v_freq = 60000, + .vsync = 60, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1600, + .h_total = 1800, + .h_blank = 200, + .h_front = 24, + .h_sync = 80, + .h_back = 96, + .v_active = 900, + .v_total = 1000, + .v_blank = 100, + .v_front = 1, + .v_sync = 3, + .v_back = 96, + .v_sync_ln = 1, + }, + .hdmitx_vinfo = { + .name = "1600x900p60hz", + .mode = VMODE_HDMI, + .width = 1600, + .height = 900, + .field_height = 900, + .aspect_ratio_num = 16, + .aspect_ratio_den = 9, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 108000000, + .htotal = 1800, + .vtotal = 1000, + .fr_adj_type = VOUT_FR_ADJ_HDMI, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1600x1200p60_4x3 = { + .vic = HDMIV_1600x1200p60hz, + .name = "1600x1200p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 162000, + .timing = { + .pixel_freq = 162000, + .h_freq = 75000, + .v_freq = 60000, + .vsync = 60, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1600, + .h_total = 2160, + .h_blank = 560, + .h_front = 64, + .h_sync = 192, + .h_back = 304, + .v_active = 1200, + .v_total = 1250, + .v_blank = 50, + .v_front = 1, + .v_sync = 3, + .v_back = 46, + .v_sync_ln = 1, + }, + .hdmitx_vinfo = { + .name = "1600x1200p60hz", + .mode = VMODE_HDMI, + .width = 1600, + .height = 1200, + .field_height = 1200, + .aspect_ratio_num = 4, + .aspect_ratio_den = 3, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 162000000, + .htotal = 2160, + .vtotal = 1250, + .fr_adj_type = VOUT_FR_ADJ_HDMI, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1680x1050p60_8x5 = { + .vic = HDMIV_1680x1050p60hz, + .name = "1680x1050p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 146250, + .timing = { + .pixel_freq = 146250, + .h_freq = 65340, + .v_freq = 59954, + .vsync = 60, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1680, + .h_total = 2240, + .h_blank = 560, + .h_front = 104, + .h_sync = 176, + .h_back = 280, + .v_active = 1050, + .v_total = 1089, + .v_blank = 39, + .v_front = 3, + .v_sync = 6, + .v_back = 30, + .v_sync_ln = 1, + }, + .hdmitx_vinfo = { + .name = "1680x1050p60hz", + .mode = VMODE_HDMI, + .width = 1680, + .height = 1050, + .field_height = 1050, + .aspect_ratio_num = 8, + .aspect_ratio_den = 5, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 146250000, + .htotal = 2240, + .vtotal = 1089, + .fr_adj_type = VOUT_FR_ADJ_HDMI, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1920x1200p60_8x5 = { + .vic = HDMIV_1920x1200p60hz, + .name = "1920x1200p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 193250, + .timing = { + .pixel_freq = 193250, + .h_freq = 74700, + .v_freq = 59885, + .vsync = 60, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1920, + .h_total = 2592, + .h_blank = 672, + .h_front = 136, + .h_sync = 200, + .h_back = 336, + .v_active = 1200, + .v_total = 1245, + .v_blank = 45, + .v_front = 3, + .v_sync = 6, + .v_back = 36, + .v_sync_ln = 1, + }, + .hdmitx_vinfo = { + .name = "1920x1200p60hz", + .mode = VMODE_HDMI, + .width = 1920, + .height = 1200, + .field_height = 1200, + .aspect_ratio_num = 8, + .aspect_ratio_den = 5, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 193250000, + .htotal = 2592, + .vtotal = 1245, + .fr_adj_type = VOUT_FR_ADJ_HDMI, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_2160x1200p90_9x5 = { + .vic = HDMIV_2160x1200p90hz, + .name = "2160x1200p90hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 268550, + .timing = { + .pixel_freq = 268550, + .h_freq = 109080, + .v_freq = 90000, + .vsync = 90, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 2160, + .h_total = 2462, + .h_blank = 302, + .h_front = 190, + .h_sync = 32, + .h_back = 80, + .v_active = 1200, + .v_total = 1212, + .v_blank = 12, + .v_front = 6, + .v_sync = 3, + .v_back = 3, + .v_sync_ln = 1, + }, + .hdmitx_vinfo = { + .name = "2160x1200p90hz", + .mode = VMODE_HDMI, + .width = 2160, + .height = 1200, + .field_height = 1200, + .aspect_ratio_num = 9, + .aspect_ratio_den = 5, + .sync_duration_num = 90, + .sync_duration_den = 1, + .video_clk = 268550000, + .htotal = 2462, + .vtotal = 1212, + .fr_adj_type = VOUT_FR_ADJ_HDMI, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_2560x1600p60_8x5 = { + .vic = HDMIV_2560x1600p60hz, + .name = "2560x1600p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 348500, + .timing = { + .pixel_freq = 348500, + .h_freq = 99458, + .v_freq = 59987, + .vsync = 60, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 2560, + .h_total = 3504, + .h_blank = 944, + .h_front = 192, + .h_sync = 280, + .h_back = 472, + .v_active = 1600, + .v_total = 1658, + .v_blank = 58, + .v_front = 3, + .v_sync = 6, + .v_back = 49, + .v_sync_ln = 1, + }, + .hdmitx_vinfo = { + .name = "2560x1600p60hz", + .mode = VMODE_HDMI, + .width = 2560, + .height = 1600, + .field_height = 1600, + .aspect_ratio_num = 8, + .aspect_ratio_den = 5, + .sync_duration_num = 60, + .sync_duration_den = 1, + .video_clk = 348500000, + .htotal = 3504, + .vtotal = 1658, + .fr_adj_type = VOUT_FR_ADJ_HDMI, + .viu_color_fmt = COLOR_FMT_YUV444, + .viu_mux = VIU_MUX_ENCP, + }, +}; static struct hdmi_format_para *all_fmt_paras[] = { &fmt_para_3840x2160p60_16x9, @@ -1415,6 +2612,31 @@ static struct hdmi_format_para *all_fmt_paras[] = { &fmt_para_4096x2160p60_256x135_y420, &fmt_para_3840x2160p50_16x9_y420, &fmt_para_4096x2160p50_256x135_y420, + &fmt_para_2560x1080p50_64x27, + &fmt_para_2560x1080p60_64x27, + &fmt_para_vesa_640x480p60_4x3, + &fmt_para_vesa_800x480p60_4x3, + &fmt_para_vesa_800x600p60_4x3, + &fmt_para_vesa_852x480p60_213x120, + &fmt_para_vesa_854x480p60_427x240, + &fmt_para_vesa_1024x600p60_17x10, + &fmt_para_vesa_1024x768p60_4x3, + &fmt_para_vesa_1152x864p75_4x3, + &fmt_para_vesa_1280x768p60_5x3, + &fmt_para_vesa_1280x800p60_8x5, + &fmt_para_vesa_1280x960p60_4x3, + &fmt_para_vesa_1280x1024p60_5x4, + &fmt_para_vesa_1360x768p60_16x9, + &fmt_para_vesa_1366x768p60_16x9, + &fmt_para_vesa_1400x1050p60_4x3, + &fmt_para_vesa_1440x900p60_8x5, + &fmt_para_vesa_1440x2560p60_9x16, + &fmt_para_vesa_1600x900p60_16x9, + &fmt_para_vesa_1600x1200p60_4x3, + &fmt_para_vesa_1680x1050p60_8x5, + &fmt_para_vesa_1920x1200p60_8x5, + &fmt_para_vesa_2160x1200p90_9x5, + &fmt_para_vesa_2560x1600p60_8x5, &fmt_para_null_hdmi_fmt, &fmt_para_non_hdmi_fmt, NULL, @@ -1455,6 +2677,30 @@ struct hdmi_format_para *hdmi_match_dtd_paras(struct dtd *t) return NULL; } +struct hdmi_format_para *hdmi_get_vesa_paras(struct vesa_standard_timing *t) +{ + int i; + + if (!t) + return NULL; + for (i = 0; all_fmt_paras[i] != NULL; i++) { + if ((t->hactive == all_fmt_paras[i]->timing.h_active) && + (t->vactive == all_fmt_paras[i]->timing.v_active)) { + if (t->hsync && + (t->hsync == all_fmt_paras[i]->timing.vsync)) + return all_fmt_paras[i]; + if ((t->hblank && (t->hblank == + all_fmt_paras[i]->timing.h_blank)) + && (t->vblank && (t->vblank == + all_fmt_paras[i]->timing.v_blank)) + && (t->tmds_clk && (t->tmds_clk == + all_fmt_paras[i]->tmds_clk / 10))) + return all_fmt_paras[i]; + } + } + return NULL; +} + static struct parse_cd parse_cd_[] = { {COLORDEPTH_24B, "8bit",}, {COLORDEPTH_30B, "10bit"}, diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c index 9aa4d39..d650bfc 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c @@ -121,7 +121,7 @@ static int Edid_DecodeHeader(struct hdmitx_info *info, unsigned char *buff) return ret; } -static void Edid_ParsingIDManufacturerName(struct rx_cap *pRxCap, +static void Edid_ParsingIDManufacturerName(struct rx_cap *pRXCap, unsigned char *data) { int i; @@ -141,7 +141,7 @@ static void Edid_ParsingIDManufacturerName(struct rx_cap *pRxCap, || ((brand[2] > 26) || (brand[2] == 0))) return; for (i = 0; i < 3; i++) - pRxCap->IDManufacturerName[i] = uppercase[brand[i] - 1]; + pRXCap->IDManufacturerName[i] = uppercase[brand[i] - 1]; } static void Edid_ParsingIDProductCode(struct rx_cap *pRXCap, @@ -163,31 +163,109 @@ static void Edid_ParsingIDSerialNumber(struct rx_cap *pRXCap, pRXCap->IDSerialNumber[i] = data[3-i]; } -static int Edid_find_name_block(unsigned char *data) +/* store the idx of vesa_timing[32], which is 0 */ +static void store_vesa_idx(struct rx_cap *pRXCap, enum hdmi_vic vesa_timing) { - int ret = 0; int i; - for (i = 0; i < 3; i++) { - if (data[i]) - return ret; + for (i = 0; i < VESA_MAX_TIMING; i++) { + if (!pRXCap->vesa_timing[i]) { + pRXCap->vesa_timing[i] = vesa_timing; + break; + } + + if (pRXCap->vesa_timing[i] == vesa_timing) + break; } - if (data[3] == 0xfc) - ret = 1; - return ret; + pr_info("hdmitx: reach vesa idx MAX\n"); +} + +static void Edid_EstablishedTimings(struct rx_cap *pRXCap, unsigned char *data) +{ + if (data[0] & (1 << 5)) + store_vesa_idx(pRXCap, HDMIV_640x480p60hz); + if (data[0] & (1 << 0)) + store_vesa_idx(pRXCap, HDMIV_800x600p60hz); + if (data[1] & (1 << 3)) + store_vesa_idx(pRXCap, HDMIV_1024x768p60hz); +} + +static void Edid_StandardTimingIII(struct rx_cap *pRXCap, unsigned char *data) +{ + if (data[0] & (1 << 0)) + store_vesa_idx(pRXCap, HDMIV_1152x864p75hz); + if (data[1] & (1 << 6)) + store_vesa_idx(pRXCap, HDMIV_1280x768p60hz); + if (data[1] & (1 << 2)) + store_vesa_idx(pRXCap, HDMIV_1280x960p60hz); + if (data[1] & (1 << 1)) + store_vesa_idx(pRXCap, HDMIV_1280x1024p60hz); + if (data[2] & (1 << 7)) + store_vesa_idx(pRXCap, HDMIV_1360x768p60hz); + if (data[2] & (1 << 1)) + store_vesa_idx(pRXCap, HDMIV_1400x1050p60hz); + if (data[3] & (1 << 5)) + store_vesa_idx(pRXCap, HDMIV_1680x1050p60hz); + if (data[3] & (1 << 2)) + store_vesa_idx(pRXCap, HDMIV_1600x1200p60hz); + if (data[4] & (1 << 0)) + store_vesa_idx(pRXCap, HDMIV_1920x1200p60hz); } -static void Edid_ReceiverProductNameParse(struct rx_cap *pRxCap, +static void calc_timing(unsigned char *data, struct vesa_standard_timing *t) +{ + struct hdmi_format_para *para = NULL; + + if ((data[0] < 2) && (data[1] < 2)) + return; + t->hactive = (data[0] + 31) * 8; + switch ((data[1] >> 6) & 0x3) { + case 0: + t->vactive = t->hactive * 5 / 8; + break; + case 1: + t->vactive = t->hactive * 3 / 4; + break; + case 2: + t->vactive = t->hactive * 4 / 5; + break; + case 3: + default: + t->vactive = t->hactive * 9 / 16; + break; + } + t->hsync = (data[1] & 0x3f) + 60; + para = hdmi_get_vesa_paras(t); + if (para) + t->vesa_timing = para->vic; + +} + +static void Edid_StandardTiming(struct rx_cap *pRXCap, unsigned char *data, + int max_num) +{ + int i; + struct vesa_standard_timing timing; + + for (i = 0; i < max_num; i++) { + memset(&timing, 0, sizeof(struct vesa_standard_timing)); + calc_timing(&data[i * 2], &timing); + if (timing.vesa_timing) + store_vesa_idx(pRXCap, timing.vesa_timing); + } +} + +static void Edid_ReceiverProductNameParse(struct rx_cap *pRXCap, unsigned char *data) { int i = 0; /* some Display Product name end with 0x20, not 0x0a */ while ((data[i] != 0x0a) && (data[i] != 0x20) && (i < 13)) { - pRxCap->ReceiverProductName[i] = data[i]; + pRXCap->ReceiverProductName[i] = data[i]; i++; } - pRxCap->ReceiverProductName[i] = '\0'; + pRXCap->ReceiverProductName[i] = '\0'; } void Edid_DecodeStandardTiming(struct hdmitx_info *info, @@ -1829,7 +1907,7 @@ int check_dvi_hdmi_edid_valid(unsigned char *buf) return 1; } -static void Edid_ManufactureDateParse(struct rx_cap *pRxCap, +static void Edid_ManufactureDateParse(struct rx_cap *pRXCap, unsigned char *data) { if (data == NULL) @@ -1842,20 +1920,20 @@ static void Edid_ManufactureDateParse(struct rx_cap *pRxCap, * 0xff: model year is specified */ if ((data[0] == 0) || ((data[0] >= 0x37) && (data[0] <= 0xfe))) - pRxCap->manufacture_week = 0; + pRXCap->manufacture_week = 0; else - pRxCap->manufacture_week = data[0]; + pRXCap->manufacture_week = data[0]; /* year: * 0x0~0xf: reserved * 0x10~0xff: year of manufacture, * or model year(if specified by week=0xff) */ - pRxCap->manufacture_year = + pRXCap->manufacture_year = (data[1] <= 0xf)?0:data[1]; } -static void Edid_VersionParse(struct rx_cap *pRxCap, +static void Edid_VersionParse(struct rx_cap *pRXCap, unsigned char *data) { if (data == NULL) @@ -1865,13 +1943,13 @@ static void Edid_VersionParse(struct rx_cap *pRxCap, * 0x1: edid version 1 * 0x0,0x2~0xff: reserved */ - pRxCap->edid_version = (data[0] == 0x1)?1:0; + pRXCap->edid_version = (data[0] == 0x1)?1:0; /* * 0x0~0x4: revision number * 0x5~0xff: reserved */ - pRxCap->edid_revision = (data[1] < 0x5)?data[1]:0; + pRXCap->edid_revision = (data[1] < 0x5)?data[1]:0; } static void Edid_PhyscialSizeParse(struct rx_cap *pRxCap, @@ -2013,6 +2091,94 @@ static void rxlatency_to_vinfo(struct vinfo_s *info, struct rx_cap *rx) info->rx_latency.i_aLatency = rx->i_aLatency; } +static void Edid_Descriptor_PMT(struct rx_cap *pRXCap, + struct vesa_standard_timing *t, unsigned char *data) +{ + struct hdmi_format_para *para = NULL; + + t->tmds_clk = data[0] + (data[1] << 8); + t->hactive = data[2] + (((data[4] >> 4) & 0xf) << 8); + t->hblank = data[3] + ((data[4] & 0xf) << 8); + t->vactive = data[5] + (((data[7] >> 4) & 0xf) << 8); + t->vblank = data[6] + ((data[7] & 0xf) << 8); + para = hdmi_get_vesa_paras(t); + if (para && ((para->vic) < (HDMI_3840x2160p60_64x27 + 1))) { + pRXCap->native_VIC = para->vic; + pr_info("hdmitx: get PMT vic: %d\n", para->vic); + } + if (para && ((para->vic) >= HDMITX_VESA_OFFSET)) + store_vesa_idx(pRXCap, para->vic); +} + +static void Edid_Descriptor_PMT2(struct rx_cap *pRXCap, + struct vesa_standard_timing *t, unsigned char *data) +{ + struct hdmi_format_para *para = NULL; + + t->tmds_clk = data[0] + (data[1] << 8); + t->hactive = data[2] + (((data[4] >> 4) & 0xf) << 8); + t->hblank = data[3] + ((data[4] & 0xf) << 8); + t->vactive = data[5] + (((data[7] >> 4) & 0xf) << 8); + t->vblank = data[6] + ((data[7] & 0xf) << 8); + para = hdmi_get_vesa_paras(t); + if (para && ((para->vic) >= HDMITX_VESA_OFFSET)) + store_vesa_idx(pRXCap, para->vic); +} + +static void Edid_CVT_timing_3bytes(struct rx_cap *pRXCap, + struct vesa_standard_timing *t, const unsigned char *data) +{ + struct hdmi_format_para *para = NULL; + + t->hactive = ((data[0] + (((data[1] >> 4) & 0xf) << 8)) + 1) * 2; + switch ((data[1] >> 2) & 0x3) { + case 0: + t->vactive = t->hactive * 3 / 4; + break; + case 1: + t->vactive = t->hactive * 9 / 16; + break; + case 2: + t->vactive = t->hactive * 5 / 8; + break; + case 3: + default: + t->vactive = t->hactive * 3 / 5; + break; + } + switch ((data[2] >> 5) & 0x3) { + case 0: + t->hsync = 50; + break; + case 1: + t->hsync = 60; + break; + case 2: + t->hsync = 75; + break; + case 3: + default: + t->hsync = 85; + break; + } + para = hdmi_get_vesa_paras(t); + if (para) + t->vesa_timing = para->vic; +} + +static void Edid_CVT_timing(struct rx_cap *pRXCap, unsigned char *data) +{ + int i; + struct vesa_standard_timing t; + + for (i = 0; i < 4; i++) { + memset(&t, 0, sizeof(struct vesa_standard_timing)); + Edid_CVT_timing_3bytes(pRXCap, &t, &data[i * 3]); + if (t.vesa_timing) + store_vesa_idx(pRXCap, t.vesa_timing); + } +} + int hdmitx_edid_parse(struct hdmitx_dev *hdmitx_device) { unsigned char CheckSum; @@ -2055,18 +2221,9 @@ int hdmitx_edid_parse(struct hdmitx_dev *hdmitx_device) Edid_ParsingIDManufacturerName(&hdmitx_device->RXCap, &EDID_buf[8]); Edid_ParsingIDProductCode(&hdmitx_device->RXCap, &EDID_buf[0x0A]); Edid_ParsingIDSerialNumber(&hdmitx_device->RXCap, &EDID_buf[0x0C]); - idx[0] = EDID_DETAILED_TIMING_DES_BLOCK0_POS; - idx[1] = EDID_DETAILED_TIMING_DES_BLOCK1_POS; - idx[2] = EDID_DETAILED_TIMING_DES_BLOCK2_POS; - idx[3] = EDID_DETAILED_TIMING_DES_BLOCK3_POS; - for (i = 0; i < 4; i++) { - if ((EDID_buf[idx[i]]) && (EDID_buf[idx[i] + 1])) - Edid_DTD_parsing(pRXCap, &EDID_buf[idx[i]]); - if (Edid_find_name_block(&EDID_buf[idx[i]])) - Edid_ReceiverProductNameParse(&hdmitx_device->RXCap, - &EDID_buf[idx[i]+5]); - } + Edid_EstablishedTimings(&hdmitx_device->RXCap, &EDID_buf[0x23]); + Edid_StandardTiming(&hdmitx_device->RXCap, &EDID_buf[0x26], 8); Edid_ManufactureDateParse(&hdmitx_device->RXCap, &EDID_buf[16]); @@ -2167,6 +2324,44 @@ int hdmitx_edid_parse(struct hdmitx_dev *hdmitx_device) pRXCap->preferred_mode = pRXCap->VIC[0]; } + idx[0] = EDID_DETAILED_TIMING_DES_BLOCK0_POS; + idx[1] = EDID_DETAILED_TIMING_DES_BLOCK1_POS; + idx[2] = EDID_DETAILED_TIMING_DES_BLOCK2_POS; + idx[3] = EDID_DETAILED_TIMING_DES_BLOCK3_POS; + for (i = 0; i < 4; i++) { + if ((EDID_buf[idx[i]]) && (EDID_buf[idx[i] + 1])) { + struct vesa_standard_timing t; + + memset(&t, 0, sizeof(struct vesa_standard_timing)); + if (i == 0) + Edid_Descriptor_PMT(pRXCap, &t, + &EDID_buf[idx[i]]); + if (i == 1) + Edid_Descriptor_PMT2(pRXCap, &t, + &EDID_buf[idx[i]]); + continue; + } + switch (EDID_buf[idx[i] + 3]) { + case TAG_STANDARD_TIMINGS: + Edid_StandardTiming(pRXCap, &EDID_buf[idx[i] + 5], 6); + break; + case TAG_CVT_TIMING_CODES: + Edid_CVT_timing(pRXCap, &EDID_buf[idx[i] + 6]); + break; + case TAG_ESTABLISHED_TIMING_III: + Edid_StandardTimingIII(pRXCap, &EDID_buf[idx[i] + 6]); + break; + case TAG_RANGE_LIMITS: + break; + case TAG_DISPLAY_PRODUCT_NAME_STRING: + Edid_ReceiverProductNameParse(pRXCap, + &EDID_buf[idx[i] + 5]); + break; + default: + break; + } + } + if (hdmitx_edid_search_IEEEOUI(&EDID_buf[128])) { pRXCap->IEEEOUI = 0x0c03; pr_info(EDID "find IEEEOUT\n"); @@ -2232,6 +2427,8 @@ static struct dispmode_vic dispmode_vic_tab[] = { {"1080p25hz", HDMI_1080p25}, {"1080p24hz", HDMI_1080p24}, {"1080p60hz", HDMI_1080p60}, + {"2560x1080p50hz", HDMI_2560x1080p50_64x27}, + {"2560x1080p60hz", HDMI_2560x1080p60_64x27}, {"2160p30hz", HDMI_4k2k_30}, {"2160p25hz", HDMI_4k2k_25}, {"2160p24hz", HDMI_4k2k_24}, @@ -2246,7 +2443,34 @@ static struct dispmode_vic dispmode_vic_tab[] = { {"smpte60hz", HDMI_4096x2160p60_256x135}, {"2160p60hz", HDMI_4k2k_60}, {"2160p50hz", HDMI_4k2k_50}, - + {"640x480p60hz", HDMIV_640x480p60hz}, + {"800x480p60hz", HDMIV_800x480p60hz}, + {"800x600p60hz", HDMIV_800x600p60hz}, + {"852x480p60hz", HDMIV_852x480p60hz}, + {"854x480p60hz", HDMIV_854x480p60hz}, + {"1024x600p60hz", HDMIV_1024x600p60hz}, + {"1024x768p60hz", HDMIV_1024x768p60hz}, + {"1152x864p75hz", HDMIV_1152x864p75hz}, + {"1280x600p60hz", HDMIV_1280x600p60hz}, + {"1280x768p60hz", HDMIV_1280x768p60hz}, + {"1280x800p60hz", HDMIV_1280x800p60hz}, + {"1280x960p60hz", HDMIV_1280x960p60hz}, + {"1280x1024p60hz", HDMIV_1280x1024p60hz}, + {"1280x1024", HDMIV_1280x1024p60hz}, /* alias of "1280x1024p60hz" */ + {"1360x768p60hz", HDMIV_1360x768p60hz}, + {"1366x768p60hz", HDMIV_1366x768p60hz}, + {"1400x1050p60hz", HDMIV_1400x1050p60hz}, + {"1440x900p60hz", HDMIV_1440x900p60hz}, + {"1440x2560p60hz", HDMIV_1440x2560p60hz}, + {"1600x900p60hz", HDMIV_1600x900p60hz}, + {"1600x1200p60hz", HDMIV_1600x1200p60hz}, + {"1680x1050p60hz", HDMIV_1680x1050p60hz}, + {"1920x1200p60hz", HDMIV_1920x1200p60hz}, + {"2160x1200p90hz", HDMIV_2160x1200p90hz}, + {"2560x1080p60hz", HDMIV_2560x1080p60hz}, + {"2560x1440p60hz", HDMIV_2560x1440p60hz}, + {"2560x1600p60hz", HDMIV_2560x1600p60hz}, + {"3440x1440p60hz", HDMIV_3440x1440p60hz}, }; int hdmitx_edid_VIC_support(enum hdmi_vic vic) diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c index a694be7..53c55ae 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c @@ -2152,6 +2152,8 @@ const char *disp_mode_t[] = { "1080p50hz", "1080p25hz", "1080p24hz", + "2560x1080p50hz", + "2560x1080p60hz", "2160p30hz", "2160p25hz", "2160p24hz", @@ -2162,6 +2164,34 @@ const char *disp_mode_t[] = { "smpte60hz", "2160p50hz", "2160p60hz", + /* VESA modes */ + "640x480p60hz", + "800x480p60hz", + "800x600p60hz", + "852x480p60hz", + "854x480p60hz", + "1024x600p60hz", + "1024x768p60hz", + "1152x864p75hz", + "1280x600p60hz", + "1280x768p60hz", + "1280x800p60hz", + "1280x960p60hz", + "1280x1024p60hz", + "1360x768p60hz", + "1366x768p60hz", + "1400x1050p60hz", + "1440x900p60hz", + "1440x2560p60hz", + "1600x900p60hz", + "1600x1200p60hz", + "1680x1050p60hz", + "1920x1200p60hz", + "2160x1200p90hz", + "2560x1080p60hz", + "2560x1440p60hz", + "2560x1600p60hz", + "3440x1440p60hz", NULL }; @@ -2265,6 +2295,29 @@ static ssize_t show_preferred_mode(struct device *dev, return pos; } +/* cea_cap, a clone of disp_cap */ +static ssize_t show_cea_cap(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return show_disp_cap(dev, attr, buf); +} + +static ssize_t show_vesa_cap(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int i; + struct hdmi_format_para *para = NULL; + enum hdmi_vic *vesa_t = &hdmitx_device.RXCap.vesa_timing[0]; + int pos = 0; + + for (i = 0; vesa_t[i] && i < VESA_MAX_TIMING; i++) { + para = hdmi_get_fmt_paras(vesa_t[i]); + if (para && (para->vic >= HDMITX_VESA_OFFSET)) + pos += snprintf(buf+pos, PAGE_SIZE, "%s\n", para->name); + } + return pos; +} + /**/ static int local_support_3dfp(enum hdmi_vic vic) { @@ -3380,6 +3433,8 @@ static DEVICE_ATTR(config, 0664, show_config, store_config); static DEVICE_ATTR(debug, 0200, NULL, store_debug); static DEVICE_ATTR(disp_cap, 0444, show_disp_cap, NULL); static DEVICE_ATTR(preferred_mode, 0444, show_preferred_mode, NULL); +static DEVICE_ATTR(cea_cap, 0444, show_cea_cap, NULL); +static DEVICE_ATTR(vesa_cap, 0444, show_vesa_cap, NULL); static DEVICE_ATTR(aud_cap, 0444, show_aud_cap, NULL); static DEVICE_ATTR(hdr_cap, 0444, show_hdr_cap, NULL); static DEVICE_ATTR(dv_cap, 0444, show_dv_cap, NULL); @@ -4479,6 +4534,8 @@ static int amhdmitx_probe(struct platform_device *pdev) ret = device_create_file(dev, &dev_attr_debug); ret = device_create_file(dev, &dev_attr_disp_cap); ret = device_create_file(dev, &dev_attr_preferred_mode); + ret = device_create_file(dev, &dev_attr_cea_cap); + ret = device_create_file(dev, &dev_attr_vesa_cap); ret = device_create_file(dev, &dev_attr_disp_cap_3d); ret = device_create_file(dev, &dev_attr_aud_cap); ret = device_create_file(dev, &dev_attr_hdr_cap); @@ -4580,6 +4637,8 @@ static int amhdmitx_remove(struct platform_device *pdev) device_remove_file(dev, &dev_attr_debug); device_remove_file(dev, &dev_attr_disp_cap); device_remove_file(dev, &dev_attr_preferred_mode); + device_remove_file(dev, &dev_attr_cea_cap); + device_remove_file(dev, &dev_attr_vesa_cap); device_remove_file(dev, &dev_attr_disp_cap_3d); device_remove_file(dev, &dev_attr_hdr_cap); device_remove_file(dev, &dev_attr_dv_cap); diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_video.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_video.c index 087c4b6..2c5b2e3 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_video.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_video.c @@ -490,6 +490,325 @@ static struct hdmitx_vidpara hdmi_tx_video_params[] = { .ss = SS_SCAN_UNDER, .sc = SC_SCALE_HORIZ_VERT, }, + { + .VIC = HDMI_2560x1080p50_64x27, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_16_9, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMI_2560x1080p60_64x27, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_16_9, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_640x480p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_4_3, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_800x480p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_16_9, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_800x600p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_4_3, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_854x480p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_16_9, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_852x480p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_16_9, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_1024x600p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_16_9, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_1024x768p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_4_3, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_1152x864p75hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_4_3, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_1280x600p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_16_9, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_1280x768p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_16_9, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_1280x800p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_16_9, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_1280x960p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_16_9, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_1280x1024p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_4_3, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_1360x768p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_16_9, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_1366x768p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_16_9, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_1400x1050p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_16_9, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_1440x900p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_16_9, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_1440x2560p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_16_9, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_1600x900p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_16_9, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_1600x1200p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_16_9, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_1680x1050p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_16_9, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_1920x1200p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_16_9, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_2160x1200p90hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_4_3, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_2560x1080p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_16_9, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_2560x1440p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_16_9, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_2560x1600p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_16_9, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, + { + .VIC = HDMIV_2560x1440p60hz, + .color_prefer = COLORSPACE_RGB444, + .color_depth = COLORDEPTH_24B, + .bar_info = B_BAR_VERT_HORIZ, + .repeat_time = NO_REPEAT, + .aspect_ratio = TV_ASPECT_RATIO_16_9, + .cc = CC_ITU709, + .ss = SS_SCAN_UNDER, + .sc = SC_SCALE_HORIZ_VERT, + }, }; static struct hdmitx_vidpara *hdmi_get_video_param( @@ -618,6 +937,12 @@ int hdmitx_set_display(struct hdmitx_dev *hdev, enum hdmi_vic VideoCode) pr_info(VID "rx edid only support RGB format\n"); } + if (VideoCode >= HDMITX_VESA_OFFSET) { + hdev->para->cs = COLORSPACE_RGB444; + hdev->para->cd = COLORDEPTH_24B; + pr_info("hdmitx: VESA only support RGB format\n"); + } + if (hdev->HWOp.SetDispMode(hdev) >= 0) { /* HDMI CT 7-33 DVI Sink, no HDMI VSDB nor any * other VSDB, No GB or DI expected @@ -659,6 +984,7 @@ static void hdmi_set_vend_spec_infofram(struct hdmitx_dev *hdev, int i; unsigned char VEN_DB[6]; unsigned char VEN_HB[3]; + VEN_HB[0] = 0x81; VEN_HB[1] = 0x01; VEN_HB[2] = 0x5; diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c index 8414c9f..5b7e207 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c @@ -687,6 +687,787 @@ static const struct reg_s tvregs_4k2k_smpte_60hz[] = { {P_ENCI_VIDEO_EN, 0}, {MREG_END_MARKER, 0}, }; + +static const struct reg_s tvregs_2560x1080p50hz[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + {P_VENC_DVI_SETTING, 0x000d}, + {P_ENCP_VIDEO_MAX_PXCNT, 3299}, + {P_ENCP_VIDEO_MAX_LNCNT, 1124}, + {P_ENCP_VIDEO_HSPULS_BEGIN, 44}, + {P_ENCP_VIDEO_HSPULS_END, 132}, + {P_ENCP_VIDEO_HSPULS_SWITCH, 44}, + {P_ENCP_VIDEO_HAVON_BEGIN, 192}, + {P_ENCP_VIDEO_HAVON_END, 2751}, + {P_ENCP_VIDEO_HSO_BEGIN, 0}, + {P_ENCP_VIDEO_HSO_END, 44}, + {P_ENCP_VIDEO_VSPULS_BEGIN, 220}, + {P_ENCP_VIDEO_VSPULS_END, 2140}, + {P_ENCP_VIDEO_VSPULS_BLINE, 0}, + {P_ENCP_VIDEO_VSPULS_ELINE, 4}, + {P_ENCP_VIDEO_EQPULS_BLINE, 0}, + {P_ENCP_VIDEO_EQPULS_ELINE, 4}, + {P_ENCP_VIDEO_VAVON_BLINE, 41}, + {P_ENCP_VIDEO_VAVON_ELINE, 1120}, + {P_ENCP_VIDEO_VSO_BEGIN, 79}, + {P_ENCP_VIDEO_VSO_END, 79}, + {P_ENCP_VIDEO_VSO_BLINE, 0}, + {P_ENCP_VIDEO_VSO_ELINE, 5}, + {P_ENCP_VIDEO_YFP1_HTIME, 271}, + {P_ENCP_VIDEO_YFP2_HTIME, 2190}, + {P_VENC_VIDEO_PROG_MODE, 0x100}, + {P_ENCP_VIDEO_MODE, 0x4040}, + {P_ENCP_VIDEO_MODE_ADV, 0x0018}, + {P_ENCP_VIDEO_SYNC_MODE, 0x7}, + {P_ENCP_VIDEO_YC_DLY, 0}, + {P_ENCP_VIDEO_RGB_CTRL, 2}, + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCP_VIDEO_EN, 1}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_2560x1080p60hz[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + {P_VENC_DVI_SETTING, 0x000d}, + {P_ENCP_VIDEO_MAX_PXCNT, 2999}, + {P_ENCP_VIDEO_MAX_LNCNT, 1099}, + {P_ENCP_VIDEO_HSPULS_BEGIN, 44}, + {P_ENCP_VIDEO_HSPULS_END, 132}, + {P_ENCP_VIDEO_HSPULS_SWITCH, 44}, + {P_ENCP_VIDEO_HAVON_BEGIN, 192}, + {P_ENCP_VIDEO_HAVON_END, 2751}, + {P_ENCP_VIDEO_HSO_BEGIN, 0}, + {P_ENCP_VIDEO_HSO_END, 44}, + {P_ENCP_VIDEO_VSPULS_BEGIN, 220}, + {P_ENCP_VIDEO_VSPULS_END, 2140}, + {P_ENCP_VIDEO_VSPULS_BLINE, 0}, + {P_ENCP_VIDEO_VSPULS_ELINE, 4}, + {P_ENCP_VIDEO_EQPULS_BLINE, 0}, + {P_ENCP_VIDEO_EQPULS_ELINE, 4}, + {P_ENCP_VIDEO_VAVON_BLINE, 16}, + {P_ENCP_VIDEO_VAVON_ELINE, 1095}, + {P_ENCP_VIDEO_VSO_BEGIN, 79}, + {P_ENCP_VIDEO_VSO_END, 79}, + {P_ENCP_VIDEO_VSO_BLINE, 0}, + {P_ENCP_VIDEO_VSO_ELINE, 5}, + {P_ENCP_VIDEO_YFP1_HTIME, 271}, + {P_ENCP_VIDEO_YFP2_HTIME, 2190}, + {P_VENC_VIDEO_PROG_MODE, 0x100}, + {P_ENCP_VIDEO_MODE, 0x4040}, + {P_ENCP_VIDEO_MODE_ADV, 0x0018}, + {P_ENCP_VIDEO_SYNC_MODE, 0x7}, + {P_ENCP_VIDEO_YC_DLY, 0}, + {P_ENCP_VIDEO_RGB_CTRL, 2}, + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCP_VIDEO_EN, 1}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_vesa_640x480p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x31F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x20C,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x90,}, + {P_ENCP_VIDEO_HAVON_END, 0x30F,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x23,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x202,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x60,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x2,}, + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCP_VIDEO_EN, 1,}, + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_800x600p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x41F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x273,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0xD8,}, + {P_ENCP_VIDEO_HAVON_END, 0x3F7,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x1B,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x272,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x80,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x4,}, + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCP_VIDEO_EN, 1,}, + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_800x480p60hz[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + {P_VENC_VDAC_SETTING, 0xff}, + {P_ENCP_VIDEO_MODE, 0x4040}, + {P_ENCP_VIDEO_MODE_ADV, 0x18}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x3DF}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x1F3}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0xA8}, + {P_ENCP_VIDEO_HAVON_END, 0x3C7}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x11}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x1F0}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0}, + {P_ENCP_VIDEO_HSO_END, 0x48}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E}, + {P_ENCP_VIDEO_VSO_END, 0x32}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0}, + {P_ENCP_VIDEO_VSO_ELINE, 0x7}, + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCP_VIDEO_EN, 1}, + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_vesa_852x480p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x3B3,},/*947//htotal-1*/ + {P_ENCP_VIDEO_MAX_LNCNT, 0x213,},/*531//vtotal-1*/ + {P_ENCP_VIDEO_HAVON_BEGIN, 0x38,},/*56//hblank-hfront*/ + {P_ENCP_VIDEO_HAVON_END, 0x38B,},/*907//htotal-hfront-1*/ + {P_ENCP_VIDEO_VAVON_BLINE, 0x2A,},/*42//vblank-vfront*/ + {P_ENCP_VIDEO_VAVON_ELINE, 0x209,},/*521//vtotal-vfront-1*/ + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x10,},/*16/hor sync time*/ + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x2,},/*2//ver sync time*/ + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCP_VIDEO_EN, 1,}, + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_854x480p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x3B5,},/*949//htotal-1*/ + {P_ENCP_VIDEO_MAX_LNCNT, 0x212,},/*530//vtotal-1*/ + {P_ENCP_VIDEO_HAVON_BEGIN, 0x38,},/*56//hblank-hfront*/ + {P_ENCP_VIDEO_HAVON_END, 0x38D,},/*909//htotal-hfront-1*/ + {P_ENCP_VIDEO_VAVON_BLINE, 0x29,},/*41//vblank-vfront*/ + {P_ENCP_VIDEO_VAVON_ELINE, 0x208,},/*520//vtotal-vfront-1*/ + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x10,},/*16//hor sync time*/ + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x2,},/*2//ver sync time*/ + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCP_VIDEO_EN, 1,}, + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1024x600p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x53F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x27D,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x128,}, + {P_ENCP_VIDEO_HAVON_END, 0x527,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x23,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x27A,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x88,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, + + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCP_VIDEO_EN, 1,}, + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1024x768p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x53F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x325,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x128,}, + {P_ENCP_VIDEO_HAVON_END, 0x527,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x23,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x322,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x88,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, + + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCP_VIDEO_EN, 1,}, + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1152x864p75hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x63F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x383,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x180,}, + {P_ENCP_VIDEO_HAVON_END, 0x5FF,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x23,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x382,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x80,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x3,}, + + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCP_VIDEO_EN, 1,}, + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1280x600p60hz[] = { +#if 0 + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x59F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x336,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x70,}, + {P_ENCP_VIDEO_HAVON_END, 0x56F,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x14,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x333,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x20,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, + + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCP_VIDEO_EN, 1}, + {MREG_END_MARKER, 0} +#endif +}; + +static const struct reg_s tvregs_vesa_1280x768p60hz[] = { + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x67F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x31D,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x140,}, + {P_ENCP_VIDEO_HAVON_END, 0x63F,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x1B,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x31A,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x80,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x7,}, + + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCP_VIDEO_EN, 1}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1280x800p60hz[] = { + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x59F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x336,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x70,}, + {P_ENCP_VIDEO_HAVON_END, 0x56F,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x14,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x333,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x20,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, + + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCP_VIDEO_EN, 1}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1280x960p60hz[] = { + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x707,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x3E7,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x1A8,}, + {P_ENCP_VIDEO_HAVON_END, 0x6A7,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x27,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x3E6,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x70,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x3,}, + + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCP_VIDEO_EN, 1}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1280x1024p60hz[] = { + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x697,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x429,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x168,}, + {P_ENCP_VIDEO_HAVON_END, 0x667,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x29,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x428,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x70,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x3,}, + + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCP_VIDEO_EN, 1}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1360x768p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x6FF,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x31A,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x170,}, + {P_ENCP_VIDEO_HAVON_END, 0x6BF,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x18,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x317,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x70,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, + + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCP_VIDEO_EN, 1,}, + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1366x768p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x6FF,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x31D,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x164,}, + {P_ENCP_VIDEO_HAVON_END, 0x6B9,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x1B,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x31A,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x8F,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x3,}, + + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCP_VIDEO_EN, 1,}, + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1400x1050p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x747,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x440,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x178,}, + {P_ENCP_VIDEO_HAVON_END, 0x6EF,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x24,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x43D,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x90,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x4,}, + + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCP_VIDEO_EN, 1,}, + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1440x900p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x76F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x3A5,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x180,}, + {P_ENCP_VIDEO_HAVON_END, 0x71F,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x1F,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x3A2,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x98,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, + + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCP_VIDEO_EN, 1,}, + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1440x2560p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x623,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0xA23,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x44,}, + {P_ENCP_VIDEO_HAVON_END, 0x5E3,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x14,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0xA13,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x4,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x4,}, + + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCP_VIDEO_EN, 1,}, + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1600x900p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x707,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x3E7,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0xB0,}, + {P_ENCP_VIDEO_HAVON_END, 0x6EF,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x63,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x3E6,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x50,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x3,}, + + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCP_VIDEO_EN, 1,}, + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1600x1200p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x86F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x4E1,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x1F0,}, + {P_ENCP_VIDEO_HAVON_END, 0x82F,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x31,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x4E0,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0xC0,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x3,}, + + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCP_VIDEO_EN, 1,}, + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1680x1050p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x8BF,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x440,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x1C8,}, + {P_ENCP_VIDEO_HAVON_END, 0x857,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x24,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x43D,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0xB0,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, + + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCP_VIDEO_EN, 1,}, + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1920x1200p60hz[] = { + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0xA1F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x4DC,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x218,}, + {P_ENCP_VIDEO_HAVON_END, 0x997,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x2A,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x4D9,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0xC8,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, + + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCP_VIDEO_EN, 1}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_2160x1200p90hz[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x99D,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x4BB,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x70,}, + {P_ENCP_VIDEO_HAVON_END, 0x8DF,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x6,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x4B5,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x20,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x3,}, + + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCP_VIDEO_EN, 1}, + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_vesa_2560x1600p60hz[] = { + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0xDAF,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x679,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x2F0,}, + {P_ENCP_VIDEO_HAVON_END, 0xCEF,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x37,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x676,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x118,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, + + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCP_VIDEO_EN, 1}, + {MREG_END_MARKER, 0} +}; + +#if 0 /* TODO */ +static const struct reg_s tvregs_vesa_2560x1080p60hz[] = { + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0xA1F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x4DC,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x218,}, + {P_ENCP_VIDEO_HAVON_END, 0x997,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x2A,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x4D9,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0xC8,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, + + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCP_VIDEO_EN, 1}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_2560x1440p60hz[] = { + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0xA1F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x4DC,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x218,}, + {P_ENCP_VIDEO_HAVON_END, 0x997,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x2A,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x4D9,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0xC8,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, + + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCP_VIDEO_EN, 1}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_3440x1440p60hz[] = { + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0xA1F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x4DC,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x218,}, + {P_ENCP_VIDEO_HAVON_END, 0x997,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x2A,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x4D9,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0xC8,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, + + {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCP_VIDEO_EN, 1}, + {MREG_END_MARKER, 0} +}; +#endif + struct vic_tvregs_set { enum hdmi_vic vic; const struct reg_s *reg_setting; @@ -725,6 +1506,32 @@ static struct vic_tvregs_set tvregsTab[] = { {HDMI_3840x2160p50_16x9, tvregs_4k2k_25hz}, {HDMI_3840x2160p60_16x9_Y420, tvregs_4k2k_30hz}, {HDMI_3840x2160p50_16x9_Y420, tvregs_4k2k_25hz}, + {HDMI_2560x1080p50_64x27, tvregs_2560x1080p50hz}, + {HDMI_2560x1080p60_64x27, tvregs_2560x1080p60hz}, + {HDMIV_640x480p60hz, tvregs_vesa_640x480p60hz}, + {HDMIV_800x480p60hz, tvregs_vesa_800x480p60hz}, + {HDMIV_800x600p60hz, tvregs_vesa_800x600p60hz}, + {HDMIV_852x480p60hz, tvregs_vesa_852x480p60hz}, + {HDMIV_854x480p60hz, tvregs_vesa_854x480p60hz}, + {HDMIV_1024x600p60hz, tvregs_vesa_1024x600p60hz}, + {HDMIV_1024x768p60hz, tvregs_vesa_1024x768p60hz}, + {HDMIV_1152x864p75hz, tvregs_vesa_1152x864p75hz}, + {HDMIV_1280x600p60hz, tvregs_vesa_1280x600p60hz}, + {HDMIV_1280x768p60hz, tvregs_vesa_1280x768p60hz}, + {HDMIV_1280x800p60hz, tvregs_vesa_1280x800p60hz}, + {HDMIV_1280x960p60hz, tvregs_vesa_1280x960p60hz}, + {HDMIV_1280x1024p60hz, tvregs_vesa_1280x1024p60hz}, + {HDMIV_1360x768p60hz, tvregs_vesa_1360x768p60hz}, + {HDMIV_1366x768p60hz, tvregs_vesa_1366x768p60hz}, + {HDMIV_1400x1050p60hz, tvregs_vesa_1400x1050p60hz}, + {HDMIV_1440x900p60hz, tvregs_vesa_1440x900p60hz}, + {HDMIV_1440x2560p60hz, tvregs_vesa_1440x2560p60hz}, + {HDMIV_1600x900p60hz, tvregs_vesa_1600x900p60hz}, + {HDMIV_1600x1200p60hz, tvregs_vesa_1600x1200p60hz}, + {HDMIV_1680x1050p60hz, tvregs_vesa_1680x1050p60hz}, + {HDMIV_1920x1200p60hz, tvregs_vesa_1920x1200p60hz}, + {HDMIV_2160x1200p90hz, tvregs_vesa_2160x1200p90hz}, + {HDMIV_2560x1600p60hz, tvregs_vesa_2560x1600p60hz}, }; /* diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c index d7d629c..576cb87 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c @@ -1254,6 +1254,154 @@ static void hdmi_tvenc480i_set(struct hdmitx_vidpara *param) hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 0, 1); } +static void hdmi_tvenc_vesa_set(struct hdmitx_vidpara *param) +{ + unsigned long VFIFO2VD_TO_HDMI_LATENCY = 2; + unsigned long TOTAL_PIXELS = 0, PIXEL_REPEAT_HDMI = 0, + PIXEL_REPEAT_VENC = 0, ACTIVE_PIXELS = 0; + unsigned int FRONT_PORCH = 0, HSYNC_PIXELS = 0, ACTIVE_LINES = 0, + INTERLACE_MODE = 0, TOTAL_LINES = 0, SOF_LINES = 0, + VSYNC_LINES = 0; + unsigned int LINES_F0 = 0, LINES_F1 = 0, BACK_PORCH = 0, + EOF_LINES = 0, TOTAL_FRAMES = 0; + + unsigned long total_pixels_venc = 0; + unsigned long active_pixels_venc = 0; + unsigned long front_porch_venc = 0; + unsigned long hsync_pixels_venc = 0; + + unsigned long de_h_begin = 0, de_h_end = 0; + unsigned long de_v_begin_even = 0, de_v_end_even = 0, + de_v_begin_odd = 0, de_v_end_odd = 0; + unsigned long hs_begin = 0, hs_end = 0; + unsigned long vs_adjust = 0; + unsigned long vs_bline_evn = 0, vs_eline_evn = 0, + vs_bline_odd = 0, vs_eline_odd = 0; + unsigned long vso_begin_evn = 0, vso_begin_odd = 0; + struct hdmi_format_para *vpara = NULL; + struct hdmi_cea_timing *vtiming = NULL; + + vpara = hdmi_get_fmt_paras(param->VIC); + if (vpara == NULL) { + pr_info("hdmitx: don't find Paras for VESA %d\n", param->VIC); + return; + } + + vtiming = &vpara->timing; + + INTERLACE_MODE = 0; + PIXEL_REPEAT_VENC = 0; + PIXEL_REPEAT_HDMI = 0; + ACTIVE_PIXELS = vtiming->h_active; + ACTIVE_LINES = vtiming->v_active; + LINES_F0 = vtiming->v_total; + LINES_F1 = vtiming->v_total; + FRONT_PORCH = vtiming->h_front; + HSYNC_PIXELS = vtiming->h_sync; + BACK_PORCH = vtiming->h_back; + EOF_LINES = vtiming->v_front; + VSYNC_LINES = vtiming->v_sync; + SOF_LINES = vtiming->v_back; + TOTAL_FRAMES = 4; + + TOTAL_PIXELS = (FRONT_PORCH+HSYNC_PIXELS+BACK_PORCH+ACTIVE_PIXELS); + TOTAL_LINES = (LINES_F0+(LINES_F1*INTERLACE_MODE)); + + total_pixels_venc = (TOTAL_PIXELS / (1+PIXEL_REPEAT_HDMI)) * + (1+PIXEL_REPEAT_VENC); + active_pixels_venc = (ACTIVE_PIXELS / (1+PIXEL_REPEAT_HDMI)) * + (1+PIXEL_REPEAT_VENC); + front_porch_venc = (FRONT_PORCH / (1+PIXEL_REPEAT_HDMI)) * + (1+PIXEL_REPEAT_VENC); + hsync_pixels_venc = (HSYNC_PIXELS / (1+PIXEL_REPEAT_HDMI)) * + (1+PIXEL_REPEAT_VENC); + + hd_write_reg(P_ENCP_VIDEO_MODE, hd_read_reg(P_ENCP_VIDEO_MODE)|(1<<14)); + /* Program DE timing */ + de_h_begin = modulo(hd_read_reg(P_ENCP_VIDEO_HAVON_BEGIN) + + VFIFO2VD_TO_HDMI_LATENCY, total_pixels_venc); + de_h_end = modulo(de_h_begin + active_pixels_venc, total_pixels_venc); + hd_write_reg(P_ENCP_DE_H_BEGIN, de_h_begin); /* 220 */ + hd_write_reg(P_ENCP_DE_H_END, de_h_end); /* 1660 */ + /* Program DE timing for even field */ + de_v_begin_even = hd_read_reg(P_ENCP_VIDEO_VAVON_BLINE); + de_v_end_even = de_v_begin_even + ACTIVE_LINES; + hd_write_reg(P_ENCP_DE_V_BEGIN_EVEN, de_v_begin_even); + hd_write_reg(P_ENCP_DE_V_END_EVEN, de_v_end_even); /* 522 */ + /* Program DE timing for odd field if needed */ + if (INTERLACE_MODE) { + de_v_begin_odd = to_signed( + (hd_read_reg(P_ENCP_VIDEO_OFLD_VOAV_OFST) + & 0xf0)>>4) + de_v_begin_even + (TOTAL_LINES-1)/2; + de_v_end_odd = de_v_begin_odd + ACTIVE_LINES; + hd_write_reg(P_ENCP_DE_V_BEGIN_ODD, de_v_begin_odd); + hd_write_reg(P_ENCP_DE_V_END_ODD, de_v_end_odd); + } + + /* Program Hsync timing */ + if (de_h_end + front_porch_venc >= total_pixels_venc) { + hs_begin = de_h_end + front_porch_venc - total_pixels_venc; + vs_adjust = 1; + } else { + hs_begin = de_h_end + front_porch_venc; + vs_adjust = 0; + } + hs_end = modulo(hs_begin + hsync_pixels_venc, total_pixels_venc); + hd_write_reg(P_ENCP_DVI_HSO_BEGIN, hs_begin); + hd_write_reg(P_ENCP_DVI_HSO_END, hs_end); + /* Program Vsync timing for even field */ + if (de_v_begin_even >= SOF_LINES + VSYNC_LINES + (1-vs_adjust)) + vs_bline_evn = de_v_begin_even - SOF_LINES - VSYNC_LINES - + (1-vs_adjust); + else + vs_bline_evn = TOTAL_LINES + de_v_begin_even - SOF_LINES - + VSYNC_LINES - (1-vs_adjust); + vs_eline_evn = modulo(vs_bline_evn + VSYNC_LINES, TOTAL_LINES); + hd_write_reg(P_ENCP_DVI_VSO_BLINE_EVN, vs_bline_evn); /* 5 */ + hd_write_reg(P_ENCP_DVI_VSO_ELINE_EVN, vs_eline_evn); /* 11 */ + vso_begin_evn = hs_begin; /* 1692 */ + hd_write_reg(P_ENCP_DVI_VSO_BEGIN_EVN, vso_begin_evn); /* 1692 */ + hd_write_reg(P_ENCP_DVI_VSO_END_EVN, vso_begin_evn); /* 1692 */ + /* Program Vsync timing for odd field if needed */ + if (INTERLACE_MODE) { + vs_bline_odd = de_v_begin_odd-1 - SOF_LINES - VSYNC_LINES; + vs_eline_odd = de_v_begin_odd-1 - SOF_LINES; + vso_begin_odd = modulo(hs_begin + (total_pixels_venc>>1), + total_pixels_venc); + hd_write_reg(P_ENCP_DVI_VSO_BLINE_ODD, vs_bline_odd); + hd_write_reg(P_ENCP_DVI_VSO_ELINE_ODD, vs_eline_odd); + hd_write_reg(P_ENCP_DVI_VSO_BEGIN_ODD, vso_begin_odd); + hd_write_reg(P_ENCP_DVI_VSO_END_ODD, vso_begin_odd); + } + + switch (param->VIC) { + case HDMIV_640x480p60hz: + hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | + (0 << 1) | + (0 << 2) | + (0 << 3) | + (0 << 4) | + (4 << 5) | + (0 << 8) | + (0 << 12) + ); + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); + break; + default: + hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | + (0 << 1) | /* [ 1] src_sel_encp */ + (HSYNC_POLARITY << 2) | + (VSYNC_POLARITY << 3) | + (0 << 4) | + (4 << 5) | + (0 << 8) | + (0 << 12) + ); + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); + } + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); +} + static void hdmi_tvenc_set(struct hdmitx_vidpara *param) { unsigned long VFIFO2VD_TO_HDMI_LATENCY = 2; @@ -1276,6 +1424,20 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param) unsigned long vs_adjust = 0; unsigned long vs_bline_evn = 0, vs_eline_evn = 0; unsigned long vso_begin_evn = 0; + struct hdmi_format_para *hdmi_encp_para = NULL; + struct hdmi_cea_timing *hdmi_encp_timing = NULL; + + if ((param->VIC & HDMITX_VESA_OFFSET) == HDMITX_VESA_OFFSET) { + /* VESA modes setting */ + hdmi_tvenc_vesa_set(param); + return; + } + + hdmi_encp_para = hdmi_get_fmt_paras(param->VIC); + if (hdmi_encp_para == NULL) { + pr_info("hdmitx: don't find Paras for VIC : %d\n", param->VIC); + } else { + hdmi_encp_timing = &hdmi_encp_para->timing; switch (param->VIC) { case HDMI_3840x1080p120hz: @@ -1460,6 +1622,23 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param) SOF_LINES = 36; TOTAL_FRAMES = 4; break; + case HDMI_2560x1080p50_64x27: + case HDMI_2560x1080p60_64x27: + INTERLACE_MODE = 0U; + PIXEL_REPEAT_VENC = 0; + PIXEL_REPEAT_HDMI = 0; + ACTIVE_PIXELS = hdmi_encp_timing->h_active; + ACTIVE_LINES = hdmi_encp_timing->v_active; + LINES_F0 = hdmi_encp_timing->v_total; + LINES_F1 = hdmi_encp_timing->v_total; + FRONT_PORCH = hdmi_encp_timing->h_front; + HSYNC_PIXELS = hdmi_encp_timing->h_sync; + BACK_PORCH = hdmi_encp_timing->h_back; + EOF_LINES = hdmi_encp_timing->v_front; + VSYNC_LINES = hdmi_encp_timing->v_sync; + SOF_LINES = hdmi_encp_timing->v_back; + TOTAL_FRAMES = 4; + break; default: break; } @@ -1633,6 +1812,7 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param) (param->VIC == HDMI_576p50_16x9_rpt)) hd_set_reg_bits(P_VPU_HDMI_SETTING, 3, 12, 4); hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); + } } void phy_pll_off(void) @@ -1852,6 +2032,9 @@ static void hdmitx_set_scdc(struct hdmitx_dev *hdev) else hdev->para->tmds_clk_div40 = 1; break; + case HDMIV_2560x1600p60hz: + hdev->para->tmds_clk_div40 = 0; + break; default: hdev->para->tmds_clk_div40 = 0; break; @@ -4318,9 +4501,9 @@ static void hdcptx_events_handle(unsigned long arg) pr_info("hdcp14: instat: 0x%x\n", st_flag); } - if (st_flag & (1 << 6)) { + if (st_flag & (1 << 6)) hdmitx_set_reg_bits(HDMITX_DWC_A_HDCPCFG1, 1, 1, 1); - } + if (st_flag & (1 << 7)) { hdmitx_wr_reg(HDMITX_DWC_A_APIINTCLR, 1 << 7); hdmitx_hdcp_opr(3); @@ -5372,6 +5555,12 @@ static void config_hdmi20_tx(enum hdmi_vic vic, hdmitx_wr_reg(HDMITX_DWC_FC_AVIVID, (para->vic & HDMITX_VIC_MASK)); + /* For VESA modes, set VIC as 0 */ + if (para->vic >= HDMITX_VESA_OFFSET) { + hdmitx_wr_reg(HDMITX_DWC_FC_AVIVID, 0); + hd_write_reg(P_ISA_DEBUG_REG0, para->vic); + } + /* write Audio Infoframe packet configuration */ data32 = 0; diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c index 8c8bd05..72a5809 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c @@ -757,6 +757,12 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = { HDMI_1920x1080p25_16x9, HDMI_VIC_END}, 5940000, 4, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1}, + {{HDMI_2560x1080p50_64x27, + HDMI_VIC_END}, + 3712500, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1}, + {{HDMI_2560x1080p60_64x27, + HDMI_VIC_END}, + 3960000, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1}, {{HDMI_3840x2160p30_16x9, HDMI_3840x2160p25_16x9, HDMI_3840x2160p24_16x9, @@ -780,6 +786,66 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = { {{HDMI_VIC_FAKE, HDMI_VIC_END}, 3450000, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1}, + /* pll setting for VESA modes */ + {{HDMIV_640x480p60hz, /* 4.028G / 16 = 251.75M */ + HDMI_VIC_END}, + 4028000, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_800x480p60hz, + HDMI_VIC_END}, + 4761600, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_800x600p60hz, + HDMI_VIC_END}, + 3200000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_852x480p60hz, + HDMIV_854x480p60hz, + HDMI_VIC_END}, + 4838400, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_1024x600p60hz, + HDMI_VIC_END}, + 4115866, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_1024x768p60hz, + HDMI_VIC_END}, + 5200000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_1280x768p60hz, + HDMI_VIC_END}, + 3180000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_1280x800p60hz, + HDMI_VIC_END}, + 5680000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_1152x864p75hz, + HDMIV_1280x960p60hz, + HDMIV_1280x1024p60hz, + HDMIV_1600x900p60hz, + HDMI_VIC_END}, + 4320000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_1600x1200p60hz, + HDMI_VIC_END}, + 3240000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_1360x768p60hz, + HDMIV_1366x768p60hz, + HDMI_VIC_END}, + 3420000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_1400x1050p60hz, + HDMI_VIC_END}, + 4870000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_1440x900p60hz, + HDMI_VIC_END}, + 4260000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_1440x2560p60hz, + HDMI_VIC_END}, + 4897000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_1680x1050p60hz, + HDMI_VIC_END}, + 5850000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_1920x1200p60hz, + HDMI_VIC_END}, + 3865000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_2160x1200p90hz, + HDMI_VIC_END}, + 5371100, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1}, + {{HDMIV_2560x1600p60hz, + HDMI_VIC_END}, + 3485000, 1, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, }; /* For colordepth 10bits */ @@ -809,6 +875,12 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_30[] = { HDMI_1920x1080p25_16x9, HDMI_VIC_END}, 3712500, 2, 2, 2, VID_PLL_DIV_6p25, 1, 1, 1, -1}, + {{HDMI_2560x1080p50_64x27, + HDMI_VIC_END}, + 4640625, 1, 2, 2, VID_PLL_DIV_6p25, 1, 1, 1, -1}, + {{HDMI_2560x1080p60_64x27, + HDMI_VIC_END}, + 4950000, 1, 2, 2, VID_PLL_DIV_6p25, 1, 1, 1, -1}, {{HDMI_4096x2160p60_256x135_Y420, HDMI_4096x2160p50_256x135_Y420, HDMI_3840x2160p60_16x9_Y420, @@ -850,6 +922,12 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_36[] = { HDMI_1920x1080p50_16x9, HDMI_VIC_END}, 4455000, 1, 2, 2, VID_PLL_DIV_7p5, 1, 1, 1, -1}, + {{HDMI_2560x1080p50_64x27, + HDMI_VIC_END}, + 5568750, 1, 2, 2, VID_PLL_DIV_7p5, 1, 1, 1, -1}, + {{HDMI_2560x1080p60_64x27, + HDMI_VIC_END}, + 5940000, 1, 2, 2, VID_PLL_DIV_7p5, 1, 1, 1, -1}, {{HDMI_1920x1080p30_16x9, HDMI_1920x1080p24_16x9, HDMI_1920x1080p25_16x9, diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c index 47881ff..50e5948 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c @@ -171,11 +171,9 @@ void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk) case 5940000: if (set_hpll_hclk_v1(0xf7, frac_rate ? 0x8148 : 0x10000)) break; - else if (set_hpll_hclk_v2(0x7b, 0x18000)) + if (set_hpll_hclk_v2(0x7b, 0x18000)) break; - else if (set_hpll_hclk_v3(0xf7, 0x10000)) - break; - else + if (set_hpll_hclk_v3(0xf7, 0x10000)) break; break; case 5405400: @@ -193,6 +191,18 @@ void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk) WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0); pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); break; + case 4897000: + hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004cc); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0000d560); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x43231290); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x29272000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540028); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + break; case 4455000: hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004b9); if (frac_rate) diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_gxl.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_gxl.c index e89fcc0..58cc951 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_gxl.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_gxl.c @@ -132,6 +132,18 @@ void set_gxl_hpll_clk_out(unsigned int frac_rate, unsigned int clk) WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); break; + case 5680000: + hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002ec); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb2ab); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); + break; case 5405400: hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002e1); if (frac_rate) @@ -147,6 +159,30 @@ void set_gxl_hpll_clk_out(unsigned int frac_rate, unsigned int clk) WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); break; + case 5200000: + hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002d8); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb2ab); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); + break; + case 4870000: + hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002ca); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb3ab); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); + break; case 4455000: hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002b9); if (frac_rate) @@ -177,6 +213,18 @@ void set_gxl_hpll_clk_out(unsigned int frac_rate, unsigned int clk) WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); break; + case 3485000: + hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x40000291); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb0d5); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); + break; case 3450000: hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x4000028f); hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb300); @@ -204,6 +252,18 @@ void set_gxl_hpll_clk_out(unsigned int frac_rate, unsigned int clk) WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); break; + case 3240000: + hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x40000287); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); + break; case 2970000: hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x4000027b); if (frac_rate) @@ -234,6 +294,186 @@ void set_gxl_hpll_clk_out(unsigned int frac_rate, unsigned int clk) WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); break; + case 4320000: + hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002b4); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); + break; + case 3180000: + hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x40000284); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); + break; + case 3200000: + hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x40000285); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb155); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); + break; + case 3340000: + hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x4000028b); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb0ab); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); + break; + case 3420000: + hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x4000028e); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb200); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); + break; + case 3865000: + hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002a1); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb02b); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); + break; + case 4028000: + hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002a7); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb355); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); + break; + case 4115866: + hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002a8); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb1fa); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); + break; + case 4260000: + hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002b1); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb200); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); + break; + case 4761600: + hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002c6); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb19a); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); + break; + case 4838400: + hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002c9); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb266); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); + break; + case 4897000: + hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002cc); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb02b); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); + break; + case 5371100: + hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002df); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb32f); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); + break; + case 5600000: + hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002e9); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb155); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); + break; + case 5850000: + hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x400002f3); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x800cb300); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x860f30c4); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0c8e0000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x001fa729); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x01a31500); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x1, 28, 1); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x0, 28, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL)); + break; default: pr_info("error hpll clk: %d\n", clk); break; diff --git a/include/linux/amlogic/media/vout/hdmi_tx/hdmi_common.h b/include/linux/amlogic/media/vout/hdmi_tx/hdmi_common.h index 2e14de1..d35fd9d 100644 --- a/include/linux/amlogic/media/vout/hdmi_tx/hdmi_common.h +++ b/include/linux/amlogic/media/vout/hdmi_tx/hdmi_common.h @@ -27,6 +27,8 @@ */ #define HDMITX_VIC420_OFFSET 0x100 #define HDMITX_VIC420_FAKE_OFFSET 0x200 +#define HDMITX_VESA_OFFSET 0x300 + #define HDMITX_VIC_MASK 0xff @@ -169,6 +171,33 @@ enum hdmi_vic { HDMI_VIC_Y420_MAX, HDMI_VIC_FAKE = HDMITX_VIC420_FAKE_OFFSET, + HDMIV_640x480p60hz = HDMITX_VESA_OFFSET, + HDMIV_800x480p60hz, + HDMIV_800x600p60hz, + HDMIV_852x480p60hz, + HDMIV_854x480p60hz, + HDMIV_1024x600p60hz, + HDMIV_1024x768p60hz, + HDMIV_1152x864p75hz, + HDMIV_1280x600p60hz, + HDMIV_1280x768p60hz, + HDMIV_1280x800p60hz, + HDMIV_1280x960p60hz, + HDMIV_1280x1024p60hz, + HDMIV_1360x768p60hz, + HDMIV_1366x768p60hz, + HDMIV_1400x1050p60hz, + HDMIV_1440x900p60hz, + HDMIV_1440x2560p60hz, + HDMIV_1600x900p60hz, + HDMIV_1600x1200p60hz, + HDMIV_1680x1050p60hz, + HDMIV_1920x1200p60hz, + HDMIV_2160x1200p90hz, + HDMIV_2560x1080p60hz, + HDMIV_2560x1440p60hz, + HDMIV_2560x1600p60hz, + HDMIV_3440x1440p60hz, HDMI_VIC_END, }; @@ -221,6 +250,7 @@ struct hdmi_cea_timing { unsigned int frac_freq; /* 1.001 shift */ unsigned int h_freq; /* Unit: Hz */ unsigned int v_freq; /* Unit: 0.001 Hz */ + unsigned int vsync; /* Unit: Hz, rough data */ unsigned int vsync_polarity:1; unsigned int hsync_polarity:1; unsigned short h_active; @@ -345,6 +375,7 @@ enum hdmi_aspect_ratio { TV_ASPECT_RATIO_14_9 = 0xB, TV_ASPECT_RATIO_MAX }; +struct vesa_standard_timing; struct hdmi_format_para *hdmi_get_fmt_paras(enum hdmi_vic vic); struct hdmi_format_para *hdmi_match_dtd_paras(struct dtd *t); @@ -360,6 +391,8 @@ const char *hdmi_get_str_cs(struct hdmi_format_para *para); const char *hdmi_get_str_cr(struct hdmi_format_para *para); unsigned int hdmi_get_aud_n_paras(enum hdmi_audio_fs fs, enum hdmi_color_depth cd, unsigned int tmds_clk); +struct hdmi_format_para *hdmi_get_vesa_paras(struct vesa_standard_timing *t); + /* HDMI Audio Parmeters */ /* Refer to CEA-861-D Page 88 */ @@ -576,4 +609,14 @@ struct dtd { enum hdmi_vic vic; }; +struct vesa_standard_timing { + unsigned short hactive; + unsigned short vactive; + unsigned short hblank; + unsigned short vblank; + unsigned short hsync; + unsigned short tmds_clk; /* Value = Pixel clock ?? 10,000 */ + enum hdmi_vic vesa_timing; +}; + #endif diff --git a/include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h b/include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h index 32f2367..b35a836 100644 --- a/include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h +++ b/include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h @@ -81,6 +81,7 @@ struct hdr_dynamic_struct { unsigned char support_flags; unsigned char optional_fields[20]; }; +#define VESA_MAX_TIMING 64 struct rx_cap { unsigned int native_Mode; @@ -88,6 +89,7 @@ struct rx_cap { unsigned int VIC[VIC_MAX_NUM]; unsigned int VIC_count; unsigned int native_VIC; + enum hdmi_vic vesa_timing[VESA_MAX_TIMING]; /* Max 64 */ /*audio*/ struct rx_audiocap RxAudioCap[AUD_MAX_NUM]; unsigned char AUD_count; -- 2.7.4