From c7d6448d037e2c053bcb19a8398653f1d31ca3de Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 23 Feb 2022 12:35:06 -0800 Subject: [PATCH] [DAGCombiner][TargetLowering] Pass SDValue by value to isMulAddWithConstProfitable. Internally to DAGCombiner the SDValues were passed by non-const reference despite not being modified. They were then passed by const reference to TLI. This patch passes them by value which is consistent with the vast majority of code. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D120420 --- llvm/include/llvm/CodeGen/TargetLowering.h | 4 ++-- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 10 ++++------ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 2 +- llvm/lib/Target/AArch64/AArch64ISelLowering.h | 4 ++-- llvm/lib/Target/ARM/ARMISelLowering.cpp | 4 ++-- llvm/lib/Target/ARM/ARMISelLowering.h | 4 ++-- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 ++-- llvm/lib/Target/RISCV/RISCVISelLowering.h | 4 ++-- 8 files changed, 17 insertions(+), 19 deletions(-) diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index 2e17722..fbb9767 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -2128,8 +2128,8 @@ public: /// about some cases, a default true can be returned to let the DAGCombiner /// decide. /// AddNode is (add x, c1), and ConstNode is c2. - virtual bool isMulAddWithConstProfitable(const SDValue &AddNode, - const SDValue &ConstNode) const { + virtual bool isMulAddWithConstProfitable(SDValue AddNode, + SDValue ConstNode) const { return true; } diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 4ed38c3..3544729 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -666,9 +666,8 @@ namespace { /// of folding (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2). /// MulNode is the original multiply, AddNode is (add x, c1), /// and ConstNode is c2. - bool isMulAddWithConstProfitable(SDNode *MulNode, - SDValue &AddNode, - SDValue &ConstNode); + bool isMulAddWithConstProfitable(SDNode *MulNode, SDValue AddNode, + SDValue ConstNode); /// This is a helper function for visitAND and visitZERO_EXTEND. Returns /// true if the (and (load x) c) pattern matches an extload. ExtVT returns @@ -17355,9 +17354,8 @@ SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { // (A + c1) * c3 // (A + c2) * c3 // We're checking for cases where we have common "c3 * A" expressions. -bool DAGCombiner::isMulAddWithConstProfitable(SDNode *MulNode, - SDValue &AddNode, - SDValue &ConstNode) { +bool DAGCombiner::isMulAddWithConstProfitable(SDNode *MulNode, SDValue AddNode, + SDValue ConstNode) { APInt Val; // If the add only has one use, and the target thinks the folding is diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 2fe7744..cc0e8b3 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -12905,7 +12905,7 @@ bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const { // (mul (add x, c1), c2) -> (add (mul x, c2), c2*c1) in DAGCombine, // if the folding leads to worse code. bool AArch64TargetLowering::isMulAddWithConstProfitable( - const SDValue &AddNode, const SDValue &ConstNode) const { + SDValue AddNode, SDValue ConstNode) const { // Let the DAGCombiner decide for vector types and large types. const EVT VT = AddNode.getValueType(); if (VT.isVector() || VT.getScalarSizeInBits() > 64) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h index 9bd33bf..0d2df10 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -601,8 +601,8 @@ public: bool isLegalAddImmediate(int64_t) const override; bool isLegalICmpImmediate(int64_t) const override; - bool isMulAddWithConstProfitable(const SDValue &AddNode, - const SDValue &ConstNode) const override; + bool isMulAddWithConstProfitable(SDValue AddNode, + SDValue ConstNode) const override; bool shouldConsiderGEPOffsetSplit() const override; diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index cdf5caf..f0fc3084 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -19406,8 +19406,8 @@ bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const { // Return false to prevent folding // (mul (add r, c0), c1) -> (add (mul r, c1), c0*c1) in DAGCombine, // if the folding leads to worse code. -bool ARMTargetLowering::isMulAddWithConstProfitable( - const SDValue &AddNode, const SDValue &ConstNode) const { +bool ARMTargetLowering::isMulAddWithConstProfitable(SDValue AddNode, + SDValue ConstNode) const { // Let the DAGCombiner decide for vector types and large types. const EVT VT = AddNode.getValueType(); if (VT.isVector() || VT.getScalarSizeInBits() > 32) diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h index 08ccd9d..df1dc2a 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.h +++ b/llvm/lib/Target/ARM/ARMISelLowering.h @@ -713,8 +713,8 @@ class VectorType; Align Alignment, const DataLayout &DL) const; - bool isMulAddWithConstProfitable(const SDValue &AddNode, - const SDValue &ConstNode) const override; + bool isMulAddWithConstProfitable(SDValue AddNode, + SDValue ConstNode) const override; bool alignLoopsWithOptSize() const override; diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index fbe767a..b8969a3 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -11262,8 +11262,8 @@ bool RISCVTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT, return false; } -bool RISCVTargetLowering::isMulAddWithConstProfitable( - const SDValue &AddNode, const SDValue &ConstNode) const { +bool RISCVTargetLowering::isMulAddWithConstProfitable(SDValue AddNode, + SDValue ConstNode) const { // Let the DAGCombiner decide for vectors. EVT VT = AddNode.getValueType(); if (VT.isVector()) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index 2a4fa57..6118d9b 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -497,8 +497,8 @@ public: bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override; - bool isMulAddWithConstProfitable(const SDValue &AddNode, - const SDValue &ConstNode) const override; + bool isMulAddWithConstProfitable(SDValue AddNode, + SDValue ConstNode) const override; TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; -- 2.7.4