From c7b5f014615597e59b484a7fcb14d34fb473e248 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Tue, 28 Feb 2023 16:50:01 -0500 Subject: [PATCH] agx: Only lower int64 late This is required for address arithmetic to be lowered properly for compute kernels, which may have u2u64 in the source NIR. No shader-db changes (for GLES3.0). Signed-off-by: Alyssa Rosenzweig Part-of: --- src/asahi/compiler/agx_compile.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c index 74c097b..f9fc8e4 100644 --- a/src/asahi/compiler/agx_compile.c +++ b/src/asahi/compiler/agx_compile.c @@ -1913,8 +1913,24 @@ agx_optimize_nir(nir_shader *nir, unsigned *preamble_size) NIR_PASS_V(nir, nir_opt_dce); } + /* Only lower int64 after optimizing address arithmetic, so that u2u64/i2i64 + * conversions remain. + */ + progress = false; NIR_PASS(progress, nir, nir_lower_int64); + /* If we lowered actual int64 arithmetic (not folded into the address + * calculations), then clean up after the lowering. + */ + if (progress) { + do { + progress = false; + + NIR_PASS(progress, nir, nir_opt_algebraic); + NIR_PASS(progress, nir, nir_opt_dce); + } while (progress); + } + if (likely(!(agx_debug & AGX_DBG_NOPREAMBLE))) NIR_PASS_V(nir, agx_nir_opt_preamble, preamble_size); @@ -2250,7 +2266,6 @@ agx_preprocess_nir(nir_shader *nir, bool support_lod_bias) }; NIR_PASS_V(nir, nir_lower_regs_to_ssa); - NIR_PASS_V(nir, nir_lower_int64); NIR_PASS_V(nir, nir_lower_idiv, &idiv_options); NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL, NULL); NIR_PASS_V(nir, nir_lower_load_const_to_scalar); -- 2.7.4