From c760b5da11648acf0e8191069e72188e88b5524a Mon Sep 17 00:00:00 2001 From: Sam Parker Date: Fri, 26 Jul 2019 08:15:01 +0000 Subject: [PATCH] [ARM][LowOverheadLoops] Add CPSR defs Both WhileLoopStart and LoopEnd may get turned into a cmp and br pair, so add an implicit def to these pseudo instructions in case that WLS and LE aren't generated. Differential Revision: https://reviews.llvm.org/D65275 llvm-svn: 367089 --- llvm/lib/Target/ARM/ARMInstrThumb2.td | 6 +- .../CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir | 52 +++---- .../LowOverheadLoops/end-positive-offset.mir | 170 ++++++++------------- .../CodeGen/Thumb2/LowOverheadLoops/massive.mir | 53 +++---- .../Thumb2/LowOverheadLoops/multiblock-massive.mir | 125 +++++++-------- .../Thumb2/LowOverheadLoops/revert-after-call.mir | 21 ++- .../Thumb2/LowOverheadLoops/revert-after-spill.mir | 22 ++- .../Thumb2/LowOverheadLoops/revert-non-loop.mir | 129 +++++++--------- .../Thumb2/LowOverheadLoops/revert-while.mir | 57 ++++--- .../CodeGen/Thumb2/LowOverheadLoops/size-limit.mir | 68 +++------ .../CodeGen/Thumb2/LowOverheadLoops/switch.mir | 122 +++++++-------- .../LowOverheadLoops/while-negative-offset.mir | 29 ++-- .../test/CodeGen/Thumb2/LowOverheadLoops/while.mir | 65 ++++---- 13 files changed, 421 insertions(+), 498 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index 7cbfaba..b9691ef 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -5217,11 +5217,13 @@ def t2LoopDec : t2PseudoInst<(outs GPRlr:$Rm), (ins GPRlr:$Rn, imm0_7:$size), 4, IIC_Br, []>, Sched<[WriteBr]>; -let isBranch = 1, isTerminator = 1, hasSideEffects = 1 in { +let isBranch = 1, isTerminator = 1, hasSideEffects = 1, Defs = [CPSR] in { +// Set WhileLoopStart and LoopEnd to occupy 8 bytes because they may +// get converted into t2CMP and t2Bcc. def t2WhileLoopStart : t2PseudoInst<(outs), (ins rGPR:$elts, brtarget:$target), - 4, IIC_Br, []>, + 8, IIC_Br, []>, Sched<[WriteBr]>; def t2LoopEnd : diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir index e77c19f..9ddfda6 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir @@ -1,12 +1,9 @@ -# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s -# CHECK: $lr = tMOVr $r0, 13, $noreg +# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s +# CHECK-NOT: $lr = tMOVr $r0, 13 # CHECK: $lr = t2DLS killed $r0 # CHECK: $lr = t2LEUpdate renamable $lr, %bb.1 --- | - target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main" - define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) { entry: %scevgep = getelementptr i32, i32* %q, i32 -1 @@ -14,27 +11,26 @@ call void @llvm.set.loop.iterations.i32(i32 %n) br label %while.body - while.body: + while.body: ; preds = %while.body, %entry %lsr.iv4 = phi i32* [ %scevgep5, %while.body ], [ %scevgep3, %entry ] %lsr.iv = phi i32* [ %scevgep1, %while.body ], [ %scevgep, %entry ] %0 = phi i32 [ %n, %entry ], [ %2, %while.body ] - %scevgep2 = getelementptr i32, i32* %lsr.iv, i32 1 - %scevgep6 = getelementptr i32, i32* %lsr.iv4, i32 1 - %1 = load i32, i32* %scevgep2, align 4 - store i32 %1, i32* %scevgep6, align 4 + %scevgep7 = getelementptr i32, i32* %lsr.iv, i32 1 + %scevgep4 = getelementptr i32, i32* %lsr.iv4, i32 1 + %1 = load i32, i32* %scevgep7, align 4 + store i32 %1, i32* %scevgep4, align 4 %scevgep1 = getelementptr i32, i32* %lsr.iv, i32 1 %scevgep5 = getelementptr i32, i32* %lsr.iv4, i32 1 %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1) %3 = icmp ne i32 %2, 0 br i1 %3, label %while.body, label %while.end - while.end: + while.end: ; preds = %while.body ret i32 0 } declare void @llvm.set.loop.iterations.i32(i32) #0 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0 - declare void @llvm.stackprotector(i8*, i8**) #1 attributes #0 = { noduplicate nounwind } attributes #1 = { nounwind } @@ -48,14 +44,14 @@ legalized: false regBankSelected: false selected: false failedISel: false -tracksRegLiveness: true +tracksRegLiveness: false hasWinCFI: false registers: [] -liveins: +liveins: - { reg: '$r0', virtual-reg: '' } - { reg: '$r1', virtual-reg: '' } - { reg: '$r2', virtual-reg: '' } -frameInfo: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false @@ -75,41 +71,41 @@ frameInfo: savePoint: '' restorePoint: '' fixedStack: [] -stack: +stack: - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +callSites: [] constants: [] machineFunctionInfo: {} body: | bb.0.entry: successors: %bb.1(0x80000000) - liveins: $r0, $r1, $r2, $r7, $lr - $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr + frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $r7, -8 - $lr = tMOVr $r0, 13, $noreg + $lr = tMOVr $r0, 14, $noreg t2DoLoopStart killed $r0 - renamable $r0 = t2SUBri killed renamable $r1, 4, 14, $noreg, $noreg - renamable $r1 = t2SUBri killed renamable $r2, 4, 14, $noreg, $noreg + renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg + renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg bb.1.while.body: successors: %bb.1(0x7c000000), %bb.2(0x04000000) - liveins: $lr, $r0, $r1 - renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep2) - early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep6) + renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep7) + early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep4) renamable $lr = t2LoopDec killed renamable $lr, 1 - t2LoopEnd renamable $lr, %bb.1 - t2B %bb.2, 14, $noreg + t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr + tB %bb.2, 14, $noreg bb.2.while.end: - $r0 = t2MOVi 0, 14, $noreg, $noreg - $sp = t2LDMIA_RET $sp, 14, $noreg, def $r7, def $pc, implicit killed $r0 + $r0, dead $cpsr = tMOVi8 0, 14, $noreg + tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 ... + diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir index 2712714..a163b9e 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir @@ -1,24 +1,18 @@ -# RUN: llc -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s +# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s # CHECK-NOT: DoLoopStart # CHECK-NOT: DLS -# CHECK: bb.2.for.body: +# CHECK: bb.1.for.body: # CHECK: t2CMPri $lr, 0, 14, $cpsr, implicit-def $cpsr -# CHECK: t2Bcc %bb.4, 1, $cpsr -# CHECK: tB %bb.3, 14, $noreg -# CHECK: bb.3.for.cond.cleanup: -# CHECK: bb.4.for.header: +# CHECK: t2Bcc %bb.3, 1, $cpsr +# CHECK: tB %bb.2, 14, $noreg +# CHECK: bb.2.for.cond.cleanup: +# CHECK: bb.3.for.header: ---- | - target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-unknown-unknown" - - define void @size_limit(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) #0 { +--- | + define void @size_limit(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) { entry: call void @llvm.set.loop.iterations.i32(i32 %N) - br label %for.body.preheader - - for.body.preheader: ; preds = %entry %scevgep = getelementptr i32, i32* %a, i32 -1 %scevgep4 = getelementptr i32, i32* %c, i32 -1 %scevgep8 = getelementptr i32, i32* %b, i32 -1 @@ -37,35 +31,28 @@ %scevgep10 = getelementptr i32, i32* %lsr.iv9, i32 1 %count.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %count, i32 1) %cmp = icmp ne i32 %count.next, 0 - br i1 %cmp, label %for.cond.cleanup, label %for.header + br i1 %cmp, label %for.header, label %for.cond.cleanup for.cond.cleanup: ; preds = %for.body ret void - for.header: ; preds = %for.body, %for.body.preheader - %lsr.iv9 = phi i32* [ %scevgep8, %for.body.preheader ], [ %scevgep10, %for.body ] - %lsr.iv5 = phi i32* [ %scevgep4, %for.body.preheader ], [ %scevgep6, %for.body ] - %lsr.iv1 = phi i32* [ %scevgep, %for.body.preheader ], [ %scevgep2, %for.body ] - %count = phi i32 [ %N, %for.body.preheader ], [ %count.next, %for.body ] + for.header: ; preds = %for.body, %entry + %lsr.iv9 = phi i32* [ %scevgep8, %entry ], [ %scevgep10, %for.body ] + %lsr.iv5 = phi i32* [ %scevgep4, %entry ], [ %scevgep6, %for.body ] + %lsr.iv1 = phi i32* [ %scevgep, %entry ], [ %scevgep2, %for.body ] + %count = phi i32 [ %N, %entry ], [ %count.next, %for.body ] br label %for.body } ; Function Attrs: nounwind - declare i32 @llvm.arm.space(i32, i32) #1 - + declare i32 @llvm.arm.space(i32 immarg, i32) #0 ; Function Attrs: noduplicate nounwind - declare void @llvm.set.loop.iterations.i32(i32) #2 - + declare void @llvm.set.loop.iterations.i32(i32) #1 ; Function Attrs: noduplicate nounwind - declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #2 + declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1 - ; Function Attrs: nounwind - declare void @llvm.stackprotector(i8*, i8**) #3 - - attributes #0 = { "target-features"="+lob" } - attributes #1 = { nounwind "target-features"="+lob" } - attributes #2 = { noduplicate nounwind "target-features"="+lob" } - attributes #3 = { nounwind } + attributes #0 = { nounwind } + attributes #1 = { noduplicate nounwind } ... --- @@ -79,17 +66,17 @@ failedISel: false tracksRegLiveness: false hasWinCFI: false registers: [] -liveins: +liveins: - { reg: '$r0', virtual-reg: '' } - { reg: '$r1', virtual-reg: '' } - { reg: '$r2', virtual-reg: '' } - { reg: '$r3', virtual-reg: '' } -frameInfo: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false hasPatchPoint: false - stackSize: 56 + stackSize: 40 offsetAdjustment: 0 maxAlignment: 4 adjustsStack: false @@ -104,7 +91,7 @@ frameInfo: savePoint: '' restorePoint: '' fixedStack: [] -stack: +stack: - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, stack-id: default, callee-saved-register: '', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } @@ -129,96 +116,73 @@ stack: - { id: 7, name: '', type: spill-slot, offset: -40, size: 4, alignment: 4, stack-id: default, callee-saved-register: '', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 8, name: '', type: spill-slot, offset: -44, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '', callee-saved-restored: true, - debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 9, name: '', type: spill-slot, offset: -48, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '', callee-saved-restored: true, - debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 10, name: '', type: spill-slot, offset: -52, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '', callee-saved-restored: true, - debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 11, name: '', type: spill-slot, offset: -56, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '', callee-saved-restored: true, - debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 12, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, + - { id: 8, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 13, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, + - { id: 9, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } callSites: [] constants: [] machineFunctionInfo: {} body: | bb.0.entry: - successors: %bb.1(0x80000000) + successors: %bb.3(0x80000000) - frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION offset $lr, -4 - frame-setup CFI_INSTRUCTION offset $r4, -8 - $sp = frame-setup tSUBspi $sp, 12, 14, $noreg - frame-setup CFI_INSTRUCTION def_cfa_offset 56 + frame-setup CFI_INSTRUCTION offset $r7, -8 + $sp = frame-setup tSUBspi $sp, 8, 14, $noreg + frame-setup CFI_INSTRUCTION def_cfa_offset 40 t2DoLoopStart renamable $r3 - tSTRspi killed $r3, $sp, 11, 14, $noreg :: (store 4 into %stack.0) - tSTRspi killed $r2, $sp, 10, 14, $noreg :: (store 4 into %stack.1) - tSTRspi killed $r1, $sp, 9, 14, $noreg :: (store 4 into %stack.2) - tSTRspi killed $r0, $sp, 8, 14, $noreg :: (store 4 into %stack.3) - tB %bb.1, 14, $noreg - - bb.1.for.body.preheader: - successors: %bb.4(0x80000000) - - $r0 = tLDRspi $sp, 8, 14, $noreg :: (load 4 from %stack.3) - renamable $r1, dead $cpsr = tSUBi3 killed renamable $r0, 4, 14, $noreg - $r2 = tLDRspi $sp, 10, 14, $noreg :: (load 4 from %stack.1) - renamable $r3, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg - $r12 = t2LDRi12 $sp, 36, 14, $noreg :: (load 4 from %stack.2) - renamable $lr = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg - $r4 = tLDRspi $sp, 11, 14, $noreg :: (load 4 from %stack.0) - t2STRi12 killed $lr, $sp, 28, 14, $noreg :: (store 4 into %stack.4) - tSTRspi killed $r3, $sp, 6, 14, $noreg :: (store 4 into %stack.5) - tSTRspi killed $r1, $sp, 5, 14, $noreg :: (store 4 into %stack.6) - tSTRspi killed $r4, $sp, 4, 14, $noreg :: (store 4 into %stack.7) - tB %bb.4, 14, $noreg + renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14, $noreg + renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg + renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg + tSTRspi killed $r1, $sp, 7, 14, $noreg :: (store 4 into %stack.0) + tSTRspi killed $r2, $sp, 6, 14, $noreg :: (store 4 into %stack.1) + tSTRspi killed $r0, $sp, 5, 14, $noreg :: (store 4 into %stack.2) + tSTRspi killed $r3, $sp, 4, 14, $noreg :: (store 4 into %stack.3) + tB %bb.3, 14, $noreg - bb.2.for.body: - successors: %bb.3(0x40000000), %bb.4(0x40000000) + bb.1.for.body: + successors: %bb.3(0x40000000), %bb.2(0x40000000) - $r0 = tLDRspi $sp, 3, 14, $noreg :: (load 4 from %stack.8) + $r0 = tLDRspi $sp, 3, 14, $noreg :: (load 4 from %stack.4) renamable $r1, renamable $r0 = t2LDR_PRE renamable $r0, 4, 14, $noreg :: (load 4 from %ir.scevgep11) - $r2 = tLDRspi $sp, 2, 14, $noreg :: (load 4 from %stack.9) + $r2 = tLDRspi $sp, 2, 14, $noreg :: (load 4 from %stack.5) renamable $r3, renamable $r2 = t2LDR_PRE renamable $r2, 4, 14, $noreg :: (load 4 from %ir.scevgep7) renamable $r1, dead $cpsr = nsw tMUL killed renamable $r3, killed renamable $r1, 14, $noreg - $r3 = tLDRspi $sp, 1, 14, $noreg :: (load 4 from %stack.10) + $r3 = tLDRspi $sp, 1, 14, $noreg :: (load 4 from %stack.6) early-clobber renamable $r3 = t2STR_PRE killed renamable $r1, renamable $r3, 4, 14, $noreg :: (store 4 into %ir.scevgep3) - $r1 = tLDRspi $sp, 0, 14, $noreg :: (load 4 from %stack.11) + $r1 = tLDRspi $sp, 0, 14, $noreg :: (load 4 from %stack.7) $lr = tMOVr killed $r1, 14, $noreg renamable $lr = t2LoopDec killed renamable $lr, 1 $r12 = tMOVr $lr, 14, $noreg - tSTRspi killed $r0, $sp, 7, 14, $noreg :: (store 4 into %stack.4) - tSTRspi killed $r2, $sp, 6, 14, $noreg :: (store 4 into %stack.5) - tSTRspi killed $r3, $sp, 5, 14, $noreg :: (store 4 into %stack.6) - t2STRi12 killed $r12, $sp, 16, 14, $noreg :: (store 4 into %stack.7) - t2LoopEnd killed renamable $lr, %bb.4 - tB %bb.3, 14, $noreg + tSTRspi killed $r0, $sp, 7, 14, $noreg :: (store 4 into %stack.0) + tSTRspi killed $r2, $sp, 6, 14, $noreg :: (store 4 into %stack.1) + tSTRspi killed $r3, $sp, 5, 14, $noreg :: (store 4 into %stack.2) + t2STRi12 killed $r12, $sp, 16, 14, $noreg :: (store 4 into %stack.3) + t2LoopEnd killed renamable $lr, %bb.3, implicit-def dead $cpsr + tB %bb.2, 14, $noreg - bb.3.for.cond.cleanup: - $sp = tADDspi $sp, 12, 14, $noreg - tPOP_RET 14, $noreg, def $r4, def $pc + bb.2.for.cond.cleanup: + $sp = tADDspi $sp, 8, 14, $noreg + tPOP_RET 14, $noreg, def $r7, def $pc - bb.4.for.header: - successors: %bb.2(0x80000000) + bb.3.for.header: + successors: %bb.1(0x80000000) - $r0 = tLDRspi $sp, 4, 14, $noreg :: (load 4 from %stack.7) - $r1 = tLDRspi $sp, 5, 14, $noreg :: (load 4 from %stack.6) - $r2 = tLDRspi $sp, 6, 14, $noreg :: (load 4 from %stack.5) - $r3 = tLDRspi $sp, 7, 14, $noreg :: (load 4 from %stack.4) - tSTRspi killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.11) - tSTRspi killed $r1, $sp, 1, 14, $noreg :: (store 4 into %stack.10) - tSTRspi killed $r2, $sp, 2, 14, $noreg :: (store 4 into %stack.9) - tSTRspi killed $r3, $sp, 3, 14, $noreg :: (store 4 into %stack.8) - tB %bb.2, 14, $noreg + $r0 = tLDRspi $sp, 4, 14, $noreg :: (load 4 from %stack.3) + $r1 = tLDRspi $sp, 5, 14, $noreg :: (load 4 from %stack.2) + $r2 = tLDRspi $sp, 6, 14, $noreg :: (load 4 from %stack.1) + $r3 = tLDRspi $sp, 7, 14, $noreg :: (load 4 from %stack.0) + tSTRspi killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.7) + tSTRspi killed $r1, $sp, 1, 14, $noreg :: (store 4 into %stack.6) + tSTRspi killed $r2, $sp, 2, 14, $noreg :: (store 4 into %stack.5) + tSTRspi killed $r3, $sp, 3, 14, $noreg :: (store 4 into %stack.4) + tB %bb.1, 14, $noreg ... + + diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir index aa9cbd3..b3a69b5 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir @@ -3,11 +3,7 @@ # CHECK-NOT: t2DLS # CHECK-NOT: t2LEUpdate ---- | - target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-unknown-unknown" - - ; Function Attrs: norecurse nounwind +--- | define dso_local arm_aapcscc void @massive(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) local_unnamed_addr { entry: %cmp8 = icmp eq i32 %N, 0 @@ -29,13 +25,13 @@ %lsr.iv1 = phi i32* [ %scevgep, %for.body.preheader ], [ %scevgep2, %for.body ] %0 = phi i32 [ %N, %for.body.preheader ], [ %3, %for.body ] %size = call i32 @llvm.arm.space(i32 4096, i32 undef) - %scevgep11 = getelementptr i32, i32* %lsr.iv9, i32 1 - %1 = load i32, i32* %scevgep11, align 4, !tbaa !3 - %scevgep7 = getelementptr i32, i32* %lsr.iv5, i32 1 - %2 = load i32, i32* %scevgep7, align 4, !tbaa !3 + %scevgep1 = getelementptr i32, i32* %lsr.iv9, i32 1 + %1 = load i32, i32* %scevgep1, align 4, !tbaa !3 + %scevgep5 = getelementptr i32, i32* %lsr.iv5, i32 1 + %2 = load i32, i32* %scevgep5, align 4, !tbaa !3 %mul = mul nsw i32 %2, %1 - %scevgep3 = getelementptr i32, i32* %lsr.iv1, i32 1 - store i32 %mul, i32* %scevgep3, align 4, !tbaa !3 + %scevgep9 = getelementptr i32, i32* %lsr.iv1, i32 1 + store i32 %mul, i32* %scevgep9, align 4, !tbaa !3 %scevgep2 = getelementptr i32, i32* %lsr.iv1, i32 1 %scevgep6 = getelementptr i32, i32* %lsr.iv5, i32 1 %scevgep10 = getelementptr i32, i32* %lsr.iv9, i32 1 @@ -44,12 +40,17 @@ br i1 %4, label %for.body, label %for.cond.cleanup } - declare i32 @llvm.arm.space(i32, i32) #1 - declare void @llvm.set.loop.iterations.i32(i32) #2 - declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #2 + ; Function Attrs: nounwind + declare i32 @llvm.arm.space(i32 immarg, i32) #0 + + ; Function Attrs: noduplicate nounwind + declare void @llvm.set.loop.iterations.i32(i32) #1 + + ; Function Attrs: noduplicate nounwind + declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1 - attributes #1 = { nounwind } - attributes #2 = { noduplicate nounwind } + attributes #0 = { nounwind } + attributes #1 = { noduplicate nounwind } !llvm.module.flags = !{!0, !1} !llvm.ident = !{!2} @@ -74,12 +75,12 @@ failedISel: false tracksRegLiveness: false hasWinCFI: false registers: [] -liveins: +liveins: - { reg: '$r0', virtual-reg: '' } - { reg: '$r1', virtual-reg: '' } - { reg: '$r2', virtual-reg: '' } - { reg: '$r3', virtual-reg: '' } -frameInfo: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false @@ -99,25 +100,24 @@ frameInfo: savePoint: '' restorePoint: '' fixedStack: [] -stack: +stack: - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +callSites: [] constants: [] machineFunctionInfo: {} body: | bb.0.entry: successors: %bb.1(0x80000000) - frame-setup tPUSH 14, $noreg, $r7, killed $lr, implicit-def $sp, implicit $sp + frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $r7, -8 - $r7 = frame-setup tMOVr $sp, 14, $noreg - frame-setup CFI_INSTRUCTION def_cfa_register $r7 tCMPi8 $r3, 0, 14, $noreg, implicit-def $cpsr t2IT 0, 8, implicit-def $itstate tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate @@ -131,15 +131,16 @@ body: | successors: %bb.1(0x7c000000), %bb.2(0x04000000) dead renamable $r3 = SPACE 4096, undef renamable $r0 - renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep11, !tbaa !3) - renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14, $noreg :: (load 4 from %ir.scevgep7, !tbaa !3) + renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep1, !tbaa !3) + renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14, $noreg :: (load 4 from %ir.scevgep5, !tbaa !3) renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14, $noreg - early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep3, !tbaa !3) + early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep9, !tbaa !3) renamable $lr = t2LoopDec killed renamable $lr, 1 - t2LoopEnd renamable $lr, %bb.1 + t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr tB %bb.2, 14, $noreg bb.2.for.cond.cleanup: tPOP_RET 14, $noreg, def $r7, def $pc ... + diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir index f40321b..7033ddb 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir @@ -4,61 +4,57 @@ # CHECK-NOT: t2LEUpdate --- | - target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-unknown-unknown" - define dso_local arm_aapcscc void @size_limit(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) local_unnamed_addr { entry: %cmp8 = icmp eq i32 %N, 0 br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader for.body.preheader: ; preds = %entry + call void @llvm.set.loop.iterations.i32(i32 %N) br label %for.body for.cond.cleanup: ; preds = %for.end, %entry ret void - for.body: ; preds = %for.body.preheader, %for.end + for.body: ; preds = %for.end, %for.body.preheader %lsr.iv4 = phi i32* [ %b, %for.body.preheader ], [ %scevgep5, %for.end ] %lsr.iv2 = phi i32* [ %c, %for.body.preheader ], [ %scevgep3, %for.end ] %lsr.iv1 = phi i32* [ %a, %for.body.preheader ], [ %scevgep, %for.end ] %lsr.iv = phi i32 [ %N, %for.body.preheader ], [ %lsr.iv.next, %for.end ] %size = call i32 @llvm.arm.space(i32 3072, i32 undef) - %0 = load i32, i32* %lsr.iv4, align 4, !tbaa !3 - %1 = load i32, i32* %lsr.iv2, align 4, !tbaa !3 + %0 = load i32, i32* %lsr.iv4, align 4 + %1 = load i32, i32* %lsr.iv2, align 4 %mul = mul nsw i32 %1, %0 - store i32 %mul, i32* %lsr.iv1, align 4, !tbaa !3 + store i32 %mul, i32* %lsr.iv1, align 4 %cmp = icmp ne i32 %0, 0 br i1 %cmp, label %middle.block, label %for.end middle.block: ; preds = %for.body %div = udiv i32 %1, %0 - store i32 %div, i32* %lsr.iv1, align 4, !tbaa !3 + store i32 %div, i32* %lsr.iv1, align 4 %size.1 = call i32 @llvm.arm.space(i32 1024, i32 undef) br label %for.end for.end: ; preds = %middle.block, %for.body - %lsr.iv.next = add i32 %lsr.iv, -1 %scevgep = getelementptr i32, i32* %lsr.iv1, i32 1 %scevgep3 = getelementptr i32, i32* %lsr.iv2, i32 1 %scevgep5 = getelementptr i32, i32* %lsr.iv4, i32 1 + %lsr.iv.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1) %exitcond = icmp eq i32 %lsr.iv.next, 0 br i1 %exitcond, label %for.cond.cleanup, label %for.body } - declare i32 @llvm.arm.space(i32, i32) #1 - attributes #1 = { nounwind } + ; Function Attrs: nounwind + declare i32 @llvm.arm.space(i32 immarg, i32) #0 + + ; Function Attrs: noduplicate nounwind + declare void @llvm.set.loop.iterations.i32(i32) #1 - !llvm.module.flags = !{!0, !1} - !llvm.ident = !{!2} + ; Function Attrs: noduplicate nounwind + declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1 - !0 = !{i32 1, !"wchar_size", i32 4} - !1 = !{i32 1, !"min_enum_size", i32 4} - !2 = !{!"clang version 9.0.0 (http://llvm.org/git/clang.git a9c7c0fc5d468f3d18a5c6beb697ab0d5be2ff4c) (http://llvm.org/git/llvm.git f34bff0c141a04a5182d57e2cfb1e4bc582c81b0)"} - !3 = !{!4, !4, i64 0} - !4 = !{!"int", !5, i64 0} - !5 = !{!"omnipotent char", !6, i64 0} - !6 = !{!"Simple C/C++ TBAA"} + attributes #0 = { nounwind } + attributes #1 = { noduplicate nounwind } ... --- @@ -72,18 +68,18 @@ failedISel: false tracksRegLiveness: false hasWinCFI: false registers: [] -liveins: +liveins: - { reg: '$r0', virtual-reg: '' } - { reg: '$r1', virtual-reg: '' } - { reg: '$r2', virtual-reg: '' } - { reg: '$r3', virtual-reg: '' } -frameInfo: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false hasPatchPoint: false - stackSize: 16 - offsetAdjustment: -8 + stackSize: 8 + offsetAdjustment: 0 maxAlignment: 4 adjustsStack: false hasCalls: false @@ -97,64 +93,61 @@ frameInfo: savePoint: '' restorePoint: '' fixedStack: [] -stack: +stack: - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, - debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true, - debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +callSites: [] constants: [] machineFunctionInfo: {} body: | bb.0.entry: - successors: %bb.1(0x30000000), %bb.3(0x50000000) + successors: %bb.2(0x80000000) - frame-setup tPUSH 14, $noreg, killed $r4, killed $r6, $r7, killed $lr, implicit-def $sp, implicit $sp - frame-setup CFI_INSTRUCTION def_cfa_offset 16 + frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION offset $lr, -4 - frame-setup CFI_INSTRUCTION offset $r7, -8 - frame-setup CFI_INSTRUCTION offset $r6, -12 - frame-setup CFI_INSTRUCTION offset $r4, -16 - $r7 = frame-setup tADDrSPi $sp, 2, 14, $noreg - frame-setup CFI_INSTRUCTION def_cfa $r7, 8 - tCBNZ $r3, %bb.3 - - bb.1.for.cond.cleanup: - tPOP_RET 14, $noreg, def $r4, def $r6, def $r7, def $pc + frame-setup CFI_INSTRUCTION offset $r4, -8 + tCMPi8 $r3, 0, 14, $noreg, implicit-def $cpsr + t2IT 0, 8, implicit-def $itstate + tPOP_RET 0, killed $cpsr, def $r4, def $pc, implicit killed $itstate + $lr = tMOVr $r3, 14, $noreg + t2DoLoopStart killed $r3 + tB %bb.2, 14, $noreg - bb.2.for.end: - successors: %bb.1(0x04000000), %bb.3(0x7c000000) + bb.1.for.end: + successors: %bb.4(0x04000000), %bb.2(0x7c000000) renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14, $noreg renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 4, 14, $noreg renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14, $noreg - renamable $r3, $cpsr = tSUBi8 killed renamable $r3, 1, 14, $noreg - tBcc %bb.1, 0, killed $cpsr - - bb.3.for.body: - successors: %bb.4(0x50000000), %bb.2(0x30000000) - - dead renamable $r12 = SPACE 3072, undef renamable $r0 - renamable $r12 = t2LDRi12 renamable $r1, 0, 14, $noreg :: (load 4 from %ir.lsr.iv4, !tbaa !3) - renamable $lr = t2LDRi12 renamable $r2, 0, 14, $noreg :: (load 4 from %ir.lsr.iv2, !tbaa !3) - t2CMPri renamable $r12, 0, 14, $noreg, implicit-def $cpsr - renamable $r4 = nsw t2MUL renamable $lr, renamable $r12, 14, $noreg - tSTRi killed renamable $r4, renamable $r0, 0, 14, $noreg :: (store 4 into %ir.lsr.iv1, !tbaa !3) - t2Bcc %bb.2, 0, killed $cpsr - - bb.4.middle.block: - successors: %bb.2(0x80000000) - - renamable $r4 = t2UDIV killed renamable $lr, killed renamable $r12, 14, $noreg - tSTRi killed renamable $r4, renamable $r0, 0, 14, $noreg :: (store 4 into %ir.lsr.iv1, !tbaa !3) - dead renamable $r4 = SPACE 1024, undef renamable $r0 - t2B %bb.2, 14, $noreg + renamable $lr = t2LoopDec killed renamable $lr, 1 + t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr + t2B %bb.4, 14, $noreg + + bb.2.for.body: + successors: %bb.3(0x50000000), %bb.1(0x30000000) + + dead renamable $r3 = SPACE 3072, undef renamable $r0 + renamable $r3 = tLDRi renamable $r1, 0, 14, $noreg :: (load 4 from %ir.lsr.iv4) + renamable $r12 = t2LDRi12 renamable $r2, 0, 14, $noreg :: (load 4 from %ir.lsr.iv2) + tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr + renamable $r4 = nsw t2MUL renamable $r12, renamable $r3, 14, $noreg + tSTRi killed renamable $r4, renamable $r0, 0, 14, $noreg :: (store 4 into %ir.lsr.iv1) + t2Bcc %bb.1, 0, killed $cpsr + + bb.3.middle.block: + successors: %bb.1(0x80000000) + + renamable $r3 = t2UDIV killed renamable $r12, killed renamable $r3, 14, $noreg + tSTRi killed renamable $r3, renamable $r0, 0, 14, $noreg :: (store 4 into %ir.lsr.iv1) + dead renamable $r3 = SPACE 1024, undef renamable $r0 + t2B %bb.1, 14, $noreg + + bb.4.for.cond.cleanup: + tPOP_RET 14, $noreg, def $r4, def $pc ... diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir index fd8170e..6e89662 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir @@ -5,8 +5,10 @@ # CHECK-NOT: t2LEUpdate --- | + ; ModuleID = '/home/sampar01/src/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.ll' + source_filename = "/home/sampar01/src/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.ll" target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" + target triple = "thumbv8.1m.main" define i32 @skip_spill(i32 %n) #0 { entry: @@ -32,9 +34,16 @@ } declare i32 @bar(...) local_unnamed_addr #0 + + ; Function Attrs: noduplicate nounwind declare void @llvm.set.loop.iterations.i32(i32) #1 + + ; Function Attrs: noduplicate nounwind declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1 + ; Function Attrs: nounwind + declare void @llvm.stackprotector(i8*, i8**) #2 + attributes #0 = { "target-features"="+mve.fp" } attributes #1 = { noduplicate nounwind } attributes #2 = { nounwind } @@ -51,9 +60,9 @@ failedISel: false tracksRegLiveness: false hasWinCFI: false registers: [] -liveins: +liveins: - { reg: '$r0', virtual-reg: '' } -frameInfo: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false @@ -73,7 +82,7 @@ frameInfo: savePoint: '' restorePoint: '' fixedStack: [] -stack: +stack: - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } @@ -86,6 +95,7 @@ stack: - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +callSites: [] constants: [] machineFunctionInfo: {} body: | @@ -115,7 +125,7 @@ body: | $lr = tMOVr killed $r5, 14, $noreg renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r0, 14, $noreg renamable $lr = t2LoopDec killed renamable $lr, 1 - t2LoopEnd renamable $lr, %bb.2 + t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr tB %bb.3, 14, $noreg bb.3.while.end: @@ -128,3 +138,4 @@ body: | tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 ... + diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-spill.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-spill.mir index fd8170e..e66c73b 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-spill.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-spill.mir @@ -4,10 +4,7 @@ # CHECK-NOT: t2DLS # CHECK-NOT: t2LEUpdate ---- | - target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-none-eabi" - +--- | define i32 @skip_spill(i32 %n) #0 { entry: %cmp6 = icmp eq i32 %n, 0 @@ -32,9 +29,16 @@ } declare i32 @bar(...) local_unnamed_addr #0 + + ; Function Attrs: noduplicate nounwind declare void @llvm.set.loop.iterations.i32(i32) #1 + + ; Function Attrs: noduplicate nounwind declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1 + ; Function Attrs: nounwind + declare void @llvm.stackprotector(i8*, i8**) #2 + attributes #0 = { "target-features"="+mve.fp" } attributes #1 = { noduplicate nounwind } attributes #2 = { nounwind } @@ -51,9 +55,9 @@ failedISel: false tracksRegLiveness: false hasWinCFI: false registers: [] -liveins: +liveins: - { reg: '$r0', virtual-reg: '' } -frameInfo: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false @@ -73,7 +77,7 @@ frameInfo: savePoint: '' restorePoint: '' fixedStack: [] -stack: +stack: - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } @@ -86,6 +90,7 @@ stack: - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +callSites: [] constants: [] machineFunctionInfo: {} body: | @@ -115,7 +120,7 @@ body: | $lr = tMOVr killed $r5, 14, $noreg renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r0, 14, $noreg renamable $lr = t2LoopDec killed renamable $lr, 1 - t2LoopEnd renamable $lr, %bb.2 + t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr tB %bb.3, 14, $noreg bb.3.while.end: @@ -128,3 +133,4 @@ body: | tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 ... + diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir index 4dad8f7..73c08fd9 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir @@ -3,46 +3,58 @@ # CHECK: name: non_loop # CHECK: bb.0.entry: # CHECK: tBcc %bb.2, 3 -# CHECK: tB %bb.1, 14 # CHECK: bb.1.not.preheader: # CHECK: t2CMPri $lr, 0, 14 -# CHECK: t2Bcc %bb.3, 0 +# CHECK: t2Bcc %bb.4, 0 # CHECK: tB %bb.2 -# CHECK: bb.2.while.body: +# CHECK: bb.3.while.body: # CHECK: t2CMPri $lr, 0, 14 -# CHECK: t2Bcc %bb.2, 1 -# CHECK: tB %bb.3 -# CHECK: bb.3.while.end: +# CHECK: t2Bcc %bb.3, 1 +# CHECK: tB %bb.4 +# CHECK: bb.4.while.end: --- | define void @non_loop(i16* nocapture %a, i16* nocapture readonly %b, i32 %N) { entry: %cmp = icmp ugt i32 %N, 2 - br i1 %cmp, label %not.preheader, label %while.body + br i1 %cmp, label %not.preheader, label %while.body.preheader not.preheader: ; preds = %entry %test = call i1 @llvm.test.set.loop.iterations.i32(i32 %N) - br i1 %test, label %while.body, label %while.end - - while.body: ; preds = %while.body, %not.preheader, %entry - %a.addr.06 = phi i16* [ %incdec.ptr1, %while.body ], [ %a, %entry ], [ %a, %not.preheader ] - %b.addr.05 = phi i16* [ %incdec.ptr, %while.body ], [ %b, %entry ], [ %b, %not.preheader ] - %count = phi i32 [ %count.next, %while.body ], [ %N, %entry ], [ %N, %not.preheader ] - %incdec.ptr = getelementptr inbounds i16, i16* %b.addr.05, i32 1 - %load = load i16, i16* %b.addr.05, align 2 - %incdec.ptr1 = getelementptr inbounds i16, i16* %a.addr.06, i32 1 - store i16 %load, i16* %a.addr.06, align 2 + br i1 %test, label %while.body.preheader, label %while.end + + while.body.preheader: ; preds = %entry, %not.preheader + %scevgep = getelementptr i16, i16* %a, i32 -1 + %scevgep3 = getelementptr i16, i16* %b, i32 -1 + br label %while.body + + while.body: ; preds = %while.body.preheader, %while.body + %lsr.iv4 = phi i16* [ %scevgep3, %while.body.preheader ], [ %scevgep5, %while.body ] + %lsr.iv = phi i16* [ %scevgep, %while.body.preheader ], [ %scevgep1, %while.body ] + %count = phi i32 [ %count.next, %while.body ], [ %N, %while.body.preheader ] + %scevgep2 = getelementptr i16, i16* %lsr.iv, i32 1 + %scevgep6 = getelementptr i16, i16* %lsr.iv4, i32 1 + %load = load i16, i16* %scevgep6, align 2 + store i16 %load, i16* %scevgep2, align 2 %count.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %count, i32 1) %cmp1 = icmp ne i32 %count.next, 0 + %scevgep1 = getelementptr i16, i16* %lsr.iv, i32 1 + %scevgep5 = getelementptr i16, i16* %lsr.iv4, i32 1 br i1 %cmp1, label %while.body, label %while.end while.end: ; preds = %while.body, %not.preheader ret void } + ; Function Attrs: noduplicate nounwind declare i1 @llvm.test.set.loop.iterations.i32(i32) #0 + + ; Function Attrs: noduplicate nounwind declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0 + ; Function Attrs: nounwind + declare void @llvm.stackprotector(i8*, i8**) #1 + attributes #0 = { noduplicate nounwind } attributes #1 = { nounwind } @@ -67,7 +79,7 @@ frameInfo: isReturnAddressTaken: false hasStackMap: false hasPatchPoint: false - stackSize: 32 + stackSize: 8 offsetAdjustment: 0 maxAlignment: 4 adjustsStack: false @@ -83,28 +95,10 @@ frameInfo: restorePoint: '' fixedStack: [] stack: - - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '', callee-saved-restored: true, - debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 1, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '', callee-saved-restored: true, - debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 2, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '', callee-saved-restored: true, - debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 3, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '', callee-saved-restored: true, - debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 4, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '', callee-saved-restored: true, - debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 5, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '', callee-saved-restored: true, - debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 6, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, + - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 7, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, + - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } callSites: [] @@ -118,53 +112,32 @@ body: | frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $r7, -8 - $sp = frame-setup tSUBspi $sp, 6, 14, $noreg - frame-setup CFI_INSTRUCTION def_cfa_offset 32 - tCMPi8 renamable $r2, 3, 14, $noreg, implicit-def $cpsr - $r3 = tMOVr $r0, 14, $noreg - $r12 = tMOVr $r1, 14, $noreg $lr = tMOVr $r2, 14, $noreg - tSTRspi killed $r2, $sp, 5, 14, $noreg :: (store 4 into %stack.0) - tSTRspi killed $r1, $sp, 4, 14, $noreg :: (store 4 into %stack.1) - tSTRspi killed $r0, $sp, 3, 14, $noreg :: (store 4 into %stack.2) - tSTRspi killed $r3, $sp, 2, 14, $noreg :: (store 4 into %stack.3) - t2STRi12 killed $r12, $sp, 4, 14, $noreg :: (store 4 into %stack.4) - t2STRi12 killed $lr, $sp, 0, 14, $noreg :: (store 4 into %stack.5) - tBcc %bb.2, 3, $cpsr - tB %bb.1, 14, $noreg + tCMPi8 killed $r2, 3, 14, $noreg, implicit-def $cpsr + tBcc %bb.2, 3, killed $cpsr bb.1.not.preheader: - successors: %bb.2(0x40000000), %bb.3(0x40000000) - - $r0 = tLDRspi $sp, 3, 14, $noreg :: (load 4 from %stack.2) - $r1 = tLDRspi $sp, 4, 14, $noreg :: (load 4 from %stack.1) - $r2 = tLDRspi $sp, 5, 14, $noreg :: (load 4 from %stack.0) - $r3 = tLDRspi $sp, 5, 14, $noreg :: (load 4 from %stack.0) - tSTRspi killed $r0, $sp, 2, 14, $noreg :: (store 4 into %stack.3) - tSTRspi killed $r1, $sp, 1, 14, $noreg :: (store 4 into %stack.4) - tSTRspi killed $r2, $sp, 0, 14, $noreg :: (store 4 into %stack.5) - t2WhileLoopStart killed renamable $r3, %bb.3 + successors: %bb.2(0x40000000), %bb.4(0x40000000) + + t2WhileLoopStart renamable $lr, %bb.4, implicit-def dead $cpsr tB %bb.2, 14, $noreg - bb.2.while.body: - successors: %bb.2(0x40000000), %bb.3(0x40000000) + bb.2.while.body.preheader: + successors: %bb.3(0x80000000) - $r0 = tLDRspi $sp, 0, 14, $noreg :: (load 4 from %stack.5) - $r1 = tLDRspi $sp, 1, 14, $noreg :: (load 4 from %stack.4) - $r2 = tLDRspi $sp, 2, 14, $noreg :: (load 4 from %stack.3) - renamable $r3, renamable $r1 = t2LDRH_POST renamable $r1, 2, 14, $noreg :: (load 2 from %ir.b.addr.05) - early-clobber renamable $r2 = t2STRH_POST killed renamable $r3, renamable $r2, 2, 14, $noreg :: (store 2 into %ir.a.addr.06) - $lr = tMOVr killed $r0, 14, $noreg + renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14, $noreg + renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14, $noreg + + bb.3.while.body: + successors: %bb.3(0x7c000000), %bb.4(0x04000000) + + renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14, $noreg :: (load 2 from %ir.scevgep6) + early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store 2 into %ir.scevgep2) renamable $lr = t2LoopDec killed renamable $lr, 1 - $r0 = tMOVr $lr, 14, $noreg - tSTRspi killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.5) - tSTRspi killed $r1, $sp, 1, 14, $noreg :: (store 4 into %stack.4) - tSTRspi killed $r2, $sp, 2, 14, $noreg :: (store 4 into %stack.3) - t2LoopEnd killed renamable $lr, %bb.2 - tB %bb.3, 14, $noreg - - bb.3.while.end: - $sp = tADDspi $sp, 6, 14, $noreg + t2LoopEnd renamable $lr, %bb.3, implicit-def dead $cpsr + tB %bb.4, 14, $noreg + + bb.4.while.end: tPOP_RET 14, $noreg, def $r7, def $pc ... diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir index 9a37d41..fe19567 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir @@ -11,44 +11,52 @@ # CHECK-NEXT: t2CMPri $lr, 0, 14, $cpsr # CHECK-NEXT: t2Bcc %bb.2, 1, $cpsr # CHECK-NEXT: tB %bb.3, 14 + --- | - target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main" - define void @ne_trip_count(i1 zeroext %t1, i32* nocapture %a, i32* nocapture readonly %b, i32 %N) #0 { entry: - %cmp = icmp ne i32 %N, 0 %0 = call i1 @llvm.test.set.loop.iterations.i32(i32 %N) br i1 %0, label %do.body.preheader, label %if.end do.body.preheader: ; preds = %entry + %scevgep2 = getelementptr i32, i32* %a, i32 -1 + %scevgep5 = getelementptr i32, i32* %b, i32 -1 br label %do.body do.body: ; preds = %do.body.preheader, %do.body - %i.0 = phi i32 [ %inc, %do.body ], [ 0, %do.body.preheader ] - %1 = phi i32 [ %N, %do.body.preheader ], [ %2, %do.body ] - %scevgep = getelementptr i32, i32* %b, i32 %i.0 - %scevgep1 = getelementptr i32, i32* %a, i32 %i.0 + %lsr.iv6 = phi i32* [ %scevgep5, %do.body.preheader ], [ %scevgep7, %do.body ] + %lsr.iv = phi i32* [ %scevgep2, %do.body.preheader ], [ %scevgep3, %do.body ] + %1 = phi i32 [ %2, %do.body ], [ %N, %do.body.preheader ] + %scevgep8 = getelementptr i32, i32* %lsr.iv6, i32 1 + %scevgep4 = getelementptr i32, i32* %lsr.iv, i32 1 %size = call i32 @llvm.arm.space(i32 4096, i32 undef) - %tmp = load i32, i32* %scevgep, align 4 - store i32 %tmp, i32* %scevgep1, align 4 - %inc = add nuw i32 %i.0, 1 + %tmp = load i32, i32* %scevgep8, align 4 + store i32 %tmp, i32* %scevgep4, align 4 %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %1, i32 1) %3 = icmp ne i32 %2, 0 + %scevgep3 = getelementptr i32, i32* %lsr.iv, i32 1 + %scevgep7 = getelementptr i32, i32* %lsr.iv6, i32 1 br i1 %3, label %do.body, label %if.end if.end: ; preds = %do.body, %entry ret void } - declare i32 @llvm.arm.space(i32, i32) #1 + ; Function Attrs: nounwind + declare i32 @llvm.arm.space(i32 immarg, i32) #1 + + ; Function Attrs: noduplicate nounwind declare i1 @llvm.test.set.loop.iterations.i32(i32) #2 + + ; Function Attrs: noduplicate nounwind declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #2 + ; Function Attrs: nounwind + declare void @llvm.stackprotector(i8*, i8**) #1 + attributes #0 = { "target-features"="+lob" } - attributes #1 = { nounwind "target-features"="+lob" } + attributes #1 = { nounwind } attributes #2 = { noduplicate nounwind } - attributes #3 = { nounwind } ... --- @@ -62,11 +70,11 @@ failedISel: false tracksRegLiveness: false hasWinCFI: false registers: [] -liveins: +liveins: - { reg: '$r1', virtual-reg: '' } - { reg: '$r2', virtual-reg: '' } - { reg: '$r3', virtual-reg: '' } -frameInfo: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false @@ -86,7 +94,7 @@ frameInfo: savePoint: '' restorePoint: '' fixedStack: [] -stack: +stack: - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } @@ -104,27 +112,28 @@ body: | frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $r7, -8 - t2WhileLoopStart $r3, %bb.3 + t2WhileLoopStart $r3, %bb.3, implicit-def dead $cpsr tB %bb.1, 14, $noreg bb.1.do.body.preheader: successors: %bb.2(0x80000000) + renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg + renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg $lr = tMOVr killed $r3, 14, $noreg - renamable $r0, dead $cpsr = tMOVi8 0, 14, $noreg bb.2.do.body: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - dead renamable $r3 = SPACE 4096, undef renamable $r0 - renamable $r3 = t2LDRs renamable $r2, renamable $r0, 2, 14, $noreg :: (load 4 from %ir.scevgep) - t2STRs killed renamable $r3, renamable $r1, renamable $r0, 2, 14, $noreg :: (store 4 into %ir.scevgep1) - renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 1, 14, $noreg + dead renamable $r2 = SPACE 4096, undef renamable $r0 + renamable $r2, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14, $noreg :: (load 4 from %ir.scevgep8) + early-clobber renamable $r1 = t2STR_PRE killed renamable $r2, killed renamable $r1, 4, 14, $noreg :: (store 4 into %ir.scevgep4) renamable $lr = t2LoopDec killed renamable $lr, 1 - t2LoopEnd renamable $lr, %bb.2 + t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr tB %bb.3, 14, $noreg bb.3.if.end: tPOP_RET 14, $noreg, def $r7, def $pc ... + diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir index 00255e4..92b5c75 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir @@ -4,12 +4,8 @@ # CHECK: for.body: # CHECK: $lr = t2LEUpdate renamable $lr ---- | - target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-unknown-unknown" - - ; Function Attrs: norecurse nounwind - define dso_local arm_aapcscc void @size_limit(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) local_unnamed_addr #0 { +--- | + define dso_local arm_aapcscc void @size_limit(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) { entry: %cmp8 = icmp eq i32 %N, 0 br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader @@ -30,13 +26,13 @@ %lsr.iv1 = phi i32* [ %scevgep, %for.body.preheader ], [ %scevgep2, %for.body ] %0 = phi i32 [ %N, %for.body.preheader ], [ %3, %for.body ] %size = call i32 @llvm.arm.space(i32 4070, i32 undef) - %scevgep11 = getelementptr i32, i32* %lsr.iv9, i32 1 - %1 = load i32, i32* %scevgep11, align 4, !tbaa !3 - %scevgep7 = getelementptr i32, i32* %lsr.iv5, i32 1 - %2 = load i32, i32* %scevgep7, align 4, !tbaa !3 + %scevgep1 = getelementptr i32, i32* %lsr.iv9, i32 1 + %1 = load i32, i32* %scevgep1, align 4 + %scevgep5 = getelementptr i32, i32* %lsr.iv5, i32 1 + %2 = load i32, i32* %scevgep5, align 4 %mul = mul nsw i32 %2, %1 - %scevgep3 = getelementptr i32, i32* %lsr.iv1, i32 1 - store i32 %mul, i32* %scevgep3, align 4, !tbaa !3 + %scevgep9 = getelementptr i32, i32* %lsr.iv1, i32 1 + store i32 %mul, i32* %scevgep9, align 4 %scevgep2 = getelementptr i32, i32* %lsr.iv1, i32 1 %scevgep6 = getelementptr i32, i32* %lsr.iv5, i32 1 %scevgep10 = getelementptr i32, i32* %lsr.iv9, i32 1 @@ -46,31 +42,14 @@ } ; Function Attrs: nounwind - declare i32 @llvm.arm.space(i32, i32) #1 - + declare i32 @llvm.arm.space(i32 immarg, i32) #0 ; Function Attrs: noduplicate nounwind - declare void @llvm.set.loop.iterations.i32(i32) #2 - + declare void @llvm.set.loop.iterations.i32(i32) #1 ; Function Attrs: noduplicate nounwind - declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #2 - - ; Function Attrs: nounwind - declare void @llvm.stackprotector(i8*, i8**) #1 + declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1 - attributes #0 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+ras,+soft-float,+strict-align,+thumb-mode,-crypto,-d32,-dotprod,-fp-armv8,-fp-armv8d16,-fp-armv8d16sp,-fp-armv8sp,-fp16,-fp16fml,-fp64,-fpregs,-fullfp16,-neon,-vfp2,-vfp2d16,-vfp2d16sp,-vfp2sp,-vfp3,-vfp3d16,-vfp3d16sp,-vfp3sp,-vfp4,-vfp4d16,-vfp4d16sp,-vfp4sp" "unsafe-fp-math"="false" "use-soft-float"="true" } - attributes #1 = { nounwind } - attributes #2 = { noduplicate nounwind } - - !llvm.module.flags = !{!0, !1} - !llvm.ident = !{!2} - - !0 = !{i32 1, !"wchar_size", i32 4} - !1 = !{i32 1, !"min_enum_size", i32 4} - !2 = !{!"clang version 9.0.0 (http://llvm.org/git/clang.git a9c7c0fc5d468f3d18a5c6beb697ab0d5be2ff4c) (http://llvm.org/git/llvm.git f34bff0c141a04a5182d57e2cfb1e4bc582c81b0)"} - !3 = !{!4, !4, i64 0} - !4 = !{!"int", !5, i64 0} - !5 = !{!"omnipotent char", !6, i64 0} - !6 = !{!"Simple C/C++ TBAA"} + attributes #0 = { nounwind } + attributes #1 = { noduplicate nounwind } ... --- @@ -84,12 +63,12 @@ failedISel: false tracksRegLiveness: false hasWinCFI: false registers: [] -liveins: +liveins: - { reg: '$r0', virtual-reg: '' } - { reg: '$r1', virtual-reg: '' } - { reg: '$r2', virtual-reg: '' } - { reg: '$r3', virtual-reg: '' } -frameInfo: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false @@ -109,25 +88,24 @@ frameInfo: savePoint: '' restorePoint: '' fixedStack: [] -stack: +stack: - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +callSites: [] constants: [] machineFunctionInfo: {} body: | bb.0.entry: successors: %bb.1(0x80000000) - frame-setup tPUSH 14, $noreg, $r7, killed $lr, implicit-def $sp, implicit $sp + frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $r7, -8 - $r7 = frame-setup tMOVr $sp, 14, $noreg - frame-setup CFI_INSTRUCTION def_cfa_register $r7 tCMPi8 $r3, 0, 14, $noreg, implicit-def $cpsr t2IT 0, 8, implicit-def $itstate tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate @@ -141,15 +119,17 @@ body: | successors: %bb.1(0x7c000000), %bb.2(0x04000000) dead renamable $r3 = SPACE 4070, undef renamable $r0 - renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep11, !tbaa !3) - renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14, $noreg :: (load 4 from %ir.scevgep7, !tbaa !3) + renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep1) + renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14, $noreg :: (load 4 from %ir.scevgep5) renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14, $noreg - early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep3, !tbaa !3) + early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep9) renamable $lr = t2LoopDec killed renamable $lr, 1 - t2LoopEnd renamable $lr, %bb.1 + t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr tB %bb.2, 14, $noreg bb.2.for.cond.cleanup: tPOP_RET 14, $noreg, def $r7, def $pc ... + + diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir index 052c79c..742f67a 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir @@ -6,26 +6,22 @@ # CHECK: $lr = t2LEUpdate renamable $lr, %bb.2 --- | - target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-unknown-unknown" - - ; Function Attrs: norecurse nounwind readonly - define dso_local arm_aapcscc i32 @search(i8* nocapture readonly %c, i32 %N) local_unnamed_addr #0 { + define dso_local arm_aapcscc i32 @search(i8* nocapture readonly %c, i32 %N) { entry: %cmp11 = icmp eq i32 %N, 0 br i1 %cmp11, label %for.cond.cleanup, label %for.body.preheader - for.body.preheader: + for.body.preheader: ; preds = %entry call void @llvm.set.loop.iterations.i32(i32 %N) br label %for.body - for.cond.cleanup: + for.cond.cleanup: ; preds = %for.inc, %entry %found.0.lcssa = phi i32 [ 0, %entry ], [ %found.1, %for.inc ] %spaces.0.lcssa = phi i32 [ 0, %entry ], [ %spaces.1, %for.inc ] %sub = sub nsw i32 %found.0.lcssa, %spaces.0.lcssa ret i32 %sub - for.body: + for.body: ; preds = %for.inc, %for.body.preheader %lsr.iv1 = phi i8* [ %c, %for.body.preheader ], [ %scevgep, %for.inc ] %spaces.013 = phi i32 [ %spaces.1, %for.inc ], [ 0, %for.body.preheader ] %found.012 = phi i32 [ %found.1, %for.inc ], [ 0, %for.body.preheader ] @@ -39,15 +35,15 @@ i32 32, label %sw.bb1 ] - sw.bb: + sw.bb: ; preds = %for.body, %for.body, %for.body %inc = add nsw i32 %found.012, 1 br label %for.inc - sw.bb1: + sw.bb1: ; preds = %for.body %inc2 = add nsw i32 %spaces.013, 1 br label %for.inc - for.inc: + for.inc: ; preds = %sw.bb1, %sw.bb, %for.body %found.1 = phi i32 [ %found.012, %for.body ], [ %found.012, %sw.bb1 ], [ %inc, %sw.bb ] %spaces.1 = phi i32 [ %spaces.013, %for.body ], [ %inc2, %sw.bb1 ], [ %spaces.013, %sw.bb ] %scevgep = getelementptr i8, i8* %lsr.iv1, i32 1 @@ -58,9 +54,6 @@ declare void @llvm.set.loop.iterations.i32(i32) #1 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1 - declare void @llvm.stackprotector(i8*, i8**) #2 - - attributes #0 = { norecurse nounwind readonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+ras,+soft-float,+strict-align,+thumb-mode,-crypto,-d32,-dotprod,-fp-armv8,-fp-armv8d16,-fp-armv8d16sp,-fp-armv8sp,-fp16,-fp16fml,-fp64,-fpregs,-fullfp16,-neon,-vfp2,-vfp2d16,-vfp2d16sp,-vfp2sp,-vfp3,-vfp3d16,-vfp3d16sp,-vfp3sp,-vfp4,-vfp4d16,-vfp4d16sp,-vfp4sp" "unsafe-fp-math"="false" "use-soft-float"="true" } attributes #1 = { noduplicate nounwind } attributes #2 = { nounwind } @@ -73,13 +66,13 @@ legalized: false regBankSelected: false selected: false failedISel: false -tracksRegLiveness: true +tracksRegLiveness: false hasWinCFI: false registers: [] -liveins: +liveins: - { reg: '$r0', virtual-reg: '' } - { reg: '$r1', virtual-reg: '' } -frameInfo: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false @@ -99,7 +92,7 @@ frameInfo: savePoint: '' restorePoint: '' fixedStack: [] -stack: +stack: - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } @@ -112,87 +105,78 @@ stack: - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +callSites: [] constants: [] machineFunctionInfo: {} body: | bb.0.entry: - successors: %bb.1(0x30000000), %bb.3(0x50000000) - liveins: $r0, $r1, $r4, $r6, $lr + successors: %bb.7(0x30000000), %bb.1(0x50000000) - $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r6, $r7, killed $lr + frame-setup tPUSH 14, $noreg, killed $r4, killed $r6, $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup CFI_INSTRUCTION def_cfa_offset 16 frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r6, -12 frame-setup CFI_INSTRUCTION offset $r4, -16 - $r7 = frame-setup t2ADDri $sp, 8, 14, $noreg, $noreg + $r7 = frame-setup tADDrSPi $sp, 2, 14, $noreg frame-setup CFI_INSTRUCTION def_cfa $r7, 8 - t2CMPri $r1, 0, 14, $noreg, implicit-def $cpsr - t2Bcc %bb.1, 0, killed $cpsr + tCBZ $r1, %bb.7 - bb.3.for.body.preheader: + bb.1.for.body.preheader: successors: %bb.4(0x80000000) - liveins: $r0, $r1 $lr = tMOVr $r1, 14, $noreg t2DoLoopStart killed $r1 - renamable $r1 = t2MOVi 0, 14, $noreg, $noreg + renamable $r1, dead $cpsr = tMOVi8 0, 14, $noreg renamable $r12 = t2MOVi 1, 14, $noreg, $noreg - renamable $r2 = t2MOVi 0, 14, $noreg, $noreg + renamable $r2, dead $cpsr = tMOVi8 0, 14, $noreg + tB %bb.4, 14, $noreg - bb.4.for.body: - successors: %bb.5(0x26666665), %bb.6(0x5999999b) - liveins: $lr, $r0, $r1, $r2, $r12 + bb.2.for.body: + successors: %bb.3(0x80000000) - renamable $r3 = t2LDRBi12 renamable $r0, 0, 14, $noreg :: (load 1 from %ir.lsr.iv1) - renamable $r4 = t2SUBri renamable $r3, 108, 14, $noreg, $noreg - renamable $lr = t2LoopDec killed renamable $lr, 1 - t2CMPri renamable $r4, 4, 14, $noreg, implicit-def $cpsr - t2Bcc %bb.5, 8, killed $cpsr + tCMPi8 killed renamable $r3, 32, 14, $noreg, implicit-def $cpsr + t2IT 0, 8, implicit-def $itstate + renamable $r1 = nsw tADDi8 $noreg, killed renamable $r1, 1, 0, killed $cpsr, implicit $r1, implicit killed $itstate - bb.6.for.body: - successors: %bb.7(0x6db6db6e), %bb.5(0x12492492) - liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r12 + bb.3.for.inc: + successors: %bb.4(0x7c000000), %bb.8(0x04000000) - renamable $r4 = t2LSLrr renamable $r12, killed renamable $r4, 14, $noreg, $noreg - t2TSTri killed renamable $r4, 25, 14, $noreg, implicit-def $cpsr - t2Bcc %bb.5, 0, killed $cpsr + renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 1, 14, $noreg + renamable $lr = t2LoopDec killed renamable $lr, 1 + t2LoopEnd renamable $lr, %bb.4, implicit-def dead $cpsr + tB %bb.8, 14, $noreg - bb.7.sw.bb: - successors: %bb.8(0x80000000) - liveins: $lr, $r0, $r1, $r2, $r12 + bb.4.for.body: + successors: %bb.2(0x26666665), %bb.5(0x5999999b) - renamable $r2 = nsw t2ADDri killed renamable $r2, 1, 14, $noreg, $noreg - t2B %bb.8, 14, $noreg + renamable $r3 = tLDRBi renamable $r0, 0, 14, $noreg :: (load 1 from %ir.lsr.iv1) + renamable $r4 = t2SUBri renamable $r3, 108, 14, $noreg, $noreg + tCMPi8 renamable $r4, 4, 14, $noreg, implicit-def $cpsr + tBcc %bb.2, 8, killed $cpsr bb.5.for.body: - successors: %bb.8(0x80000000) - liveins: $lr, $r0, $r1, $r2, $r3, $r12 + successors: %bb.6(0x6db6db6e), %bb.2(0x12492492) - t2CMPri killed renamable $r3, 32, 14, $noreg, implicit-def $cpsr - BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $r1, implicit killed $cpsr { - t2IT 0, 8, implicit-def $itstate - renamable $r1 = nsw t2ADDri killed renamable $r1, 1, 0, killed $cpsr, $noreg, implicit $r1, implicit internal killed $itstate - } + renamable $r4 = t2LSLrr renamable $r12, killed renamable $r4, 14, $noreg, $noreg + t2TSTri killed renamable $r4, 25, 14, $noreg, implicit-def $cpsr + tBcc %bb.2, 0, killed $cpsr - bb.8.for.inc: - successors: %bb.4(0x7c000000), %bb.2(0x04000000) - liveins: $lr, $r0, $r1, $r2, $r12 + bb.6.sw.bb: + successors: %bb.3(0x80000000) - renamable $r0 = t2ADDri killed renamable $r0, 1, 14, $noreg, $noreg - t2LoopEnd renamable $lr, %bb.4 - t2B %bb.2, 14, $noreg + renamable $r2, dead $cpsr = nsw tADDi8 killed renamable $r2, 1, 14, $noreg + tB %bb.3, 14, $noreg - bb.2.for.cond.cleanup: - liveins: $r1, $r2 + bb.7: + successors: %bb.8(0x80000000) - renamable $r0 = nsw t2SUBrr killed renamable $r2, killed renamable $r1, 14, $noreg, $noreg - $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r6, def $r7, def $pc, implicit killed $r0 + renamable $r2, dead $cpsr = tMOVi8 0, 14, $noreg + renamable $r1, dead $cpsr = tMOVi8 0, 14, $noreg - bb.1: - renamable $r2 = t2MOVi 0, 14, $noreg, $noreg - renamable $r1 = t2MOVi 0, 14, $noreg, $noreg - renamable $r0 = nsw t2SUBrr killed renamable $r2, killed renamable $r1, 14, $noreg, $noreg - $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r6, def $r7, def $pc, implicit killed $r0 + bb.8.for.cond.cleanup: + renamable $r0, dead $cpsr = nsw tSUBrr killed renamable $r2, killed renamable $r1, 14, $noreg + tPOP_RET 14, $noreg, def $r4, def $r6, def $r7, def $pc, implicit killed $r0 ... + diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir index 0095f8d..c32303b 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir @@ -1,8 +1,9 @@ -# RUN: llc -run-pass=arm-low-overhead-loops -o - -verify-machineinstrs %s | FileCheck %s +# RUN: llc -O0 -run-pass=arm-low-overhead-loops -o - -verify-machineinstrs %s | FileCheck %s # CHECK-NOT: WLS # CHECK-NOT: WhileLoopStart --- | + ; ModuleID = '/home/sampar01/src/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.ll' source_filename = "while-size-limit.ll" target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "thumbv8.1m.main" @@ -45,21 +46,15 @@ } ; Function Attrs: nounwind - declare i32 @llvm.arm.space(i32, i32) #1 - + declare i32 @llvm.arm.space(i32 immarg, i32) #1 ; Function Attrs: noduplicate nounwind declare i1 @llvm.test.set.loop.iterations.i32(i32) #2 - ; Function Attrs: noduplicate nounwind declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #2 - ; Function Attrs: nounwind - declare void @llvm.stackprotector(i8*, i8**) #3 - attributes #0 = { "target-features"="+lob" } - attributes #1 = { nounwind "target-features"="+lob" } - attributes #2 = { noduplicate nounwind "target-features"="+lob" } - attributes #3 = { nounwind } + attributes #1 = { nounwind } + attributes #2 = { noduplicate nounwind } ... --- @@ -73,12 +68,12 @@ failedISel: false tracksRegLiveness: false hasWinCFI: false registers: [] -liveins: +liveins: - { reg: '$r0', virtual-reg: '' } - { reg: '$r1', virtual-reg: '' } - { reg: '$r2', virtual-reg: '' } - { reg: '$r3', virtual-reg: '' } -frameInfo: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false @@ -98,7 +93,7 @@ frameInfo: savePoint: '' restorePoint: '' fixedStack: [] -stack: +stack: - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, stack-id: default, callee-saved-register: '', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } @@ -186,14 +181,16 @@ body: | tSTRspi killed $r1, $sp, 1, 14, $noreg :: (store 4 into %stack.6) tSTRspi killed $r2, $sp, 2, 14, $noreg :: (store 4 into %stack.5) tSTRspi killed $r3, $sp, 3, 14, $noreg :: (store 4 into %stack.4) - t2LoopEnd killed renamable $lr, %bb.3 + t2LoopEnd killed renamable $lr, %bb.3, implicit-def dead $cpsr tB %bb.1, 14, $noreg bb.4.while: successors: %bb.2(0x40000000), %bb.1(0x40000000) $r0 = tLDRspi $sp, 7, 14, $noreg :: (load 4 from %stack.0) - t2WhileLoopStart killed renamable $r0, %bb.2 - tB %bb.1, 14, $noreg + t2WhileLoopStart killed renamable $r0, %bb.1, implicit-def dead $cpsr + tB %bb.2, 14, $noreg ... + + diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir index 19c8fa2..8839bfb 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir @@ -2,6 +2,7 @@ # TODO: Remove the lr = tMOVr # CHECK: body: +# CHECK: entry: # CHECK: $lr = t2WLS $r2, [[EXIT:%bb[.0-9]+]] # CHECK: [[PREHEADER:bb[.0-9a-z]+]]: # CHECK: $lr = tMOVr killed $r2 @@ -9,49 +10,53 @@ # CHECK: $lr = t2LEUpdate renamable $lr --- | + ; ModuleID = '/home/sampar01/src/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.ll' + source_filename = "/home/sampar01/src/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.ll" target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv8.1m.main-arm-unknown" + target triple = "thumbv8.1m.main" - ; Function Attrs: norecurse nounwind optsize define dso_local arm_aapcscc void @copy(i16* nocapture %a, i16* nocapture readonly %b, i32 %N) { entry: - %cmp4 = icmp eq i32 %N, 0 %0 = call i1 @llvm.test.set.loop.iterations.i32(i32 %N) br i1 %0, label %while.body.preheader, label %while.end while.body.preheader: ; preds = %entry + %scevgep = getelementptr i16, i16* %a, i32 -1 + %scevgep3 = getelementptr i16, i16* %b, i32 -1 br label %while.body - while.body: ; preds = %while.body, %while.body.preheader - %a.addr.06 = phi i16* [ %incdec.ptr1, %while.body ], [ %a, %while.body.preheader ] - %b.addr.05 = phi i16* [ %incdec.ptr, %while.body ], [ %b, %while.body.preheader ] - %1 = phi i32 [ %N, %while.body.preheader ], [ %3, %while.body ] - %incdec.ptr = getelementptr inbounds i16, i16* %b.addr.05, i32 1 - %2 = load i16, i16* %b.addr.05, align 2, !tbaa !3 - %incdec.ptr1 = getelementptr inbounds i16, i16* %a.addr.06, i32 1 - store i16 %2, i16* %a.addr.06, align 2, !tbaa !3 + while.body: ; preds = %while.body.preheader, %while.body + %lsr.iv4 = phi i16* [ %scevgep3, %while.body.preheader ], [ %scevgep5, %while.body ] + %lsr.iv = phi i16* [ %scevgep, %while.body.preheader ], [ %scevgep1, %while.body ] + %1 = phi i32 [ %3, %while.body ], [ %N, %while.body.preheader ] + %scevgep2 = getelementptr i16, i16* %lsr.iv, i32 1 + %scevgep6 = getelementptr i16, i16* %lsr.iv4, i32 1 + %2 = load i16, i16* %scevgep6, align 2, !tbaa !2 + store i16 %2, i16* %scevgep2, align 2, !tbaa !2 %3 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %1, i32 1) %4 = icmp ne i32 %3, 0 + %scevgep1 = getelementptr i16, i16* %lsr.iv, i32 1 + %scevgep5 = getelementptr i16, i16* %lsr.iv4, i32 1 br i1 %4, label %while.body, label %while.end while.end: ; preds = %while.body, %entry ret void } - declare i1 @llvm.test.set.loop.iterations.i32(i32) #1 - declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1 + declare i1 @llvm.test.set.loop.iterations.i32(i32) #0 + declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0 - attributes #1 = { noduplicate nounwind } - attributes #2 = { nounwind } + attributes #0 = { noduplicate nounwind } + attributes #1 = { nounwind } !llvm.module.flags = !{!0, !1} !0 = !{i32 1, !"wchar_size", i32 4} !1 = !{i32 1, !"min_enum_size", i32 4} - !3 = !{!4, !4, i64 0} - !4 = !{!"short", !5, i64 0} - !5 = !{!"omnipotent char", !6, i64 0} - !6 = !{!"Simple C/C++ TBAA"} + !2 = !{!3, !3, i64 0} + !3 = !{!"short", !4, i64 0} + !4 = !{!"omnipotent char", !5, i64 0} + !5 = !{!"Simple C/C++ TBAA"} ... --- @@ -65,11 +70,11 @@ failedISel: false tracksRegLiveness: false hasWinCFI: false registers: [] -liveins: +liveins: - { reg: '$r0', virtual-reg: '' } - { reg: '$r1', virtual-reg: '' } - { reg: '$r2', virtual-reg: '' } -frameInfo: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false @@ -89,43 +94,45 @@ frameInfo: savePoint: '' restorePoint: '' fixedStack: [] -stack: +stack: - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +callSites: [] constants: [] machineFunctionInfo: {} body: | bb.0.entry: successors: %bb.1(0x40000000), %bb.3(0x40000000) - frame-setup tPUSH 14, $noreg, $r7, killed $lr, implicit-def $sp, implicit $sp + frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $r7, -8 - $r7 = frame-setup tMOVr $sp, 14, $noreg - frame-setup CFI_INSTRUCTION def_cfa_register $r7 - t2WhileLoopStart $r2, %bb.3 + t2WhileLoopStart $r2, %bb.3, implicit-def dead $cpsr tB %bb.1, 14, $noreg bb.1.while.body.preheader: successors: %bb.2(0x80000000) + renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14, $noreg + renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14, $noreg $lr = tMOVr killed $r2, 14, $noreg bb.2.while.body: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - renamable $r2, renamable $r1 = t2LDRH_POST killed renamable $r1, 2, 14, $noreg :: (load 2 from %ir.b.addr.05, !tbaa !3) - early-clobber renamable $r0 = t2STRH_POST killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store 2 into %ir.a.addr.06, !tbaa !3) + renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14, $noreg :: (load 2 from %ir.scevgep6, !tbaa !2) + early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store 2 into %ir.scevgep2, !tbaa !2) renamable $lr = t2LoopDec killed renamable $lr, 1 - t2LoopEnd renamable $lr, %bb.2 + t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr tB %bb.3, 14, $noreg bb.3.while.end: tPOP_RET 14, $noreg, def $r7, def $pc ... + -- 2.7.4