From c752eb4ae19710983500eef963e258b207e42df0 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 28 Feb 2022 12:59:48 -0800 Subject: [PATCH] [RISCV] Add test cases miscompile of (rotl (grevi X, 24), 16) on RV64. NFC This pattern was moved from isel to DAG combine in D119527, but it lost the RV32 qualification in the process. --- llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll index fc1aa71..c8065af 100644 --- a/llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll +++ b/llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll @@ -340,6 +340,30 @@ define i64 @grevi64(i64 %a) nounwind { ret i64 %tmp } +; FIXME: This is miscompiled. We can't fold the rotate with the grev. +define i64 @grevi64_24_rotl_16(i64 %a) nounwind { +; RV64ZBP-LABEL: grevi64_24_rotl_16: +; RV64ZBP: # %bb.0: +; RV64ZBP-NEXT: rev8.h a0, a0 +; RV64ZBP-NEXT: ret + %tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 24) + %tmp1 = call i64 @llvm.fshl.i64(i64 %tmp, i64 %tmp, i64 16) + ret i64 %tmp1 +} +declare i64 @llvm.fshl.i64(i64, i64, i64) + +; FIXME: This is miscompiled. We can't fold the rotate with the grev. +define i64 @grevi64_24_rotr_16(i64 %a) nounwind { +; RV64ZBP-LABEL: grevi64_24_rotr_16: +; RV64ZBP: # %bb.0: +; RV64ZBP-NEXT: rev8.h a0, a0 +; RV64ZBP-NEXT: ret + %tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 24) + %tmp1 = call i64 @llvm.fshr.i64(i64 %tmp, i64 %tmp, i64 16) + ret i64 %tmp1 +} +declare i64 @llvm.fshr.i64(i64, i64, i64) + define i64 @revhwi64(i64 %a) nounwind { ; RV64ZBP-LABEL: revhwi64: ; RV64ZBP: # %bb.0: -- 2.7.4