From c6cc81d61313cf875924c5bfcda801e3c0dbfd6c Mon Sep 17 00:00:00 2001 From: Bernd Edlinger Date: Wed, 19 Oct 2016 17:02:30 +0000 Subject: [PATCH] arm.c (arm_emit_coreregs_64bit_shift): Clear the result register only if "in" and "out" are different registers. 2016-10-19 Bernd Edlinger * config/arm/arm.c (arm_emit_coreregs_64bit_shift): Clear the result register only if "in" and "out" are different registers. From-SVN: r241348 --- gcc/ChangeLog | 5 +++++ gcc/config/arm/arm.c | 11 ++++++++--- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index be2521e..e4840df 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2016-10-19 Bernd Edlinger + + * config/arm/arm.c (arm_emit_coreregs_64bit_shift): Clear the result + register only if "in" and "out" are different registers. + 2016-10-19 Eric Botcazou * omp-low.c (pass_oacc_device_lower::gate): New method. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index a758839..022c1d7 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -29218,8 +29218,10 @@ arm_emit_coreregs_64bit_shift (enum rtx_code code, rtx out, rtx in, /* Clearing the out register in DImode first avoids lots of spilling and results in less stack usage. - Later this redundant insn is completely removed. */ - emit_insn (SET (out, const0_rtx)); + Later this redundant insn is completely removed. + Do that only if "in" and "out" are different registers. */ + if (REG_P (out) && REG_P (in) && REGNO (out) != REGNO (in)) + emit_insn (SET (out, const0_rtx)); emit_insn (SET (out_down, LSHIFT (code, in_down, amount))); emit_insn (SET (out_down, ORR (REV_LSHIFT (code, in_up, reverse_amount), @@ -29231,11 +29233,14 @@ arm_emit_coreregs_64bit_shift (enum rtx_code code, rtx out, rtx in, /* Shifts by a constant greater than 31. */ rtx adj_amount = GEN_INT (INTVAL (amount) - 32); - emit_insn (SET (out, const0_rtx)); + if (REG_P (out) && REG_P (in) && REGNO (out) != REGNO (in)) + emit_insn (SET (out, const0_rtx)); emit_insn (SET (out_down, SHIFT (code, in_up, adj_amount))); if (code == ASHIFTRT) emit_insn (gen_ashrsi3 (out_up, in_up, GEN_INT (31))); + else + emit_insn (SET (out_up, const0_rtx)); } } else -- 2.7.4