From c5f30727ce68da227cfba95450a358cbd75e814c Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 6 Dec 2022 12:23:30 +0100 Subject: [PATCH] arm64: dts: mt6795: Add complete CPU caches information This SoC's AP subsystem has 8x Cortex-A53 CPUs, specifically, four CPUs per cluster, with two CPU clusters. Each CPU has: - A 32KB I-cache, 2-way set associative; - A 32KB D-cache, 4-way set associative. Each cluster has a unified 1MB L2 cache, 16-way set associative. With that in mind, add the appropriate properties needed to specify the caches information for this SoC, which will now be correctly exported to sysfs. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221206112330.78431-6-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 50 ++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index bb57583..b3fc76d 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -40,6 +40,12 @@ enable-method = "psci"; reg = <0x001>; cci-control-port = <&cci_control2>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; }; @@ -49,6 +55,12 @@ enable-method = "psci"; reg = <0x002>; cci-control-port = <&cci_control2>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; }; @@ -58,6 +70,12 @@ enable-method = "psci"; reg = <0x003>; cci-control-port = <&cci_control2>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; }; @@ -67,6 +85,12 @@ enable-method = "psci"; reg = <0x100>; cci-control-port = <&cci_control1>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_1>; }; @@ -76,6 +100,12 @@ enable-method = "psci"; reg = <0x101>; cci-control-port = <&cci_control1>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_1>; }; @@ -85,6 +115,12 @@ enable-method = "psci"; reg = <0x102>; cci-control-port = <&cci_control1>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_1>; }; @@ -94,6 +130,12 @@ enable-method = "psci"; reg = <0x103>; cci-control-port = <&cci_control1>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_1>; }; @@ -138,11 +180,19 @@ l2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-unified; }; l2_1: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-unified; }; }; -- 2.7.4