From c5ae34f38f239d346090212a9f33a947a3b7642e Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Wed, 23 Sep 2015 18:59:57 -0700 Subject: [PATCH] i965: Implement nir_intrinsic_load_primitive. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Kenneth Graunke Reviewed-by: Kristian Høgsberg --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index 792663f..123e86e 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp @@ -30,6 +30,7 @@ #include "brw_fs_surface_builder.h" #include "brw_nir.h" #include "brw_fs_surface_builder.h" +#include "brw_vec4_gs_visitor.h" using namespace brw; using namespace brw::surface_access; @@ -1367,6 +1368,13 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr case nir_intrinsic_load_vertex_id: unreachable("should be lowered by lower_vertex_id()"); + case nir_intrinsic_load_primitive_id: + assert(stage == MESA_SHADER_GEOMETRY); + assert(((struct brw_gs_prog_data *)prog_data)->include_primitive_id); + bld.MOV(retype(dest, BRW_REGISTER_TYPE_UD), + retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD)); + break; + case nir_intrinsic_load_vertex_id_zero_base: case nir_intrinsic_load_base_vertex: case nir_intrinsic_load_instance_id: -- 2.7.4