From c58df88886e42174fc52ecf60be60725a53aaaa3 Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Fri, 20 Nov 2020 13:36:49 -0800 Subject: [PATCH] [AArch64][GlobalISel] Make G_EXTRACT_VECTOR_ELT of <2 x p0> legal. Also fix a selection issue for this which was using LLT::isScalar() when it should have been using !isVector(), add test for that too. --- .../AArch64/GISel/AArch64InstructionSelector.cpp | 2 +- .../Target/AArch64/GISel/AArch64LegalizerInfo.cpp | 2 +- .../CodeGen/AArch64/GlobalISel/arm64-fallback.ll | 17 -------------- .../GlobalISel/legalize-extract-vector-elt.mir | 17 ++++++++++++++ .../GlobalISel/select-extract-vector-elt.mir | 26 +++++++++++++++++++++- 5 files changed, 44 insertions(+), 20 deletions(-) diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp index c3bf873..84f1914 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp @@ -3651,7 +3651,7 @@ bool AArch64InstructionSelector::selectExtractElt( (void)WideTy; assert(WideTy.getSizeInBits() >= NarrowTy.getSizeInBits() && "source register size too small!"); - assert(NarrowTy.isScalar() && "cannot extract vector into vector!"); + assert(!NarrowTy.isVector() && "cannot extract vector into vector!"); // Need the lane index to determine the correct copy opcode. MachineOperand &LaneIdxOp = I.getOperand(2); diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp index efc82ff..cdb8256 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp @@ -589,7 +589,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) const LLT &VecTy = Query.Types[1]; return VecTy == v2s16 || VecTy == v4s16 || VecTy == v8s16 || VecTy == v4s32 || VecTy == v2s64 || VecTy == v2s32 || - VecTy == v16s8 || VecTy == v2s32; + VecTy == v16s8 || VecTy == v2s32 || VecTy == v2p0; }) .minScalarOrEltIf( [=](const LegalityQuery &Query) { diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll index 21ea67c..137e859 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll @@ -71,23 +71,6 @@ define fp128 @test_quad_dump() { ret fp128 0xL00000000000000004000000000000000 } -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: %2:_(p0) = G_EXTRACT_VECTOR_ELT %{{[0-9]+}}:_(<2 x p0>), %{{[0-9]+}}:_(s64) (in function: vector_of_pointers_extractelement) -; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_extractelement -; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_extractelement: -@var = global <2 x i16*> zeroinitializer -define void @vector_of_pointers_extractelement() { - br label %end - -block: - %dummy = extractelement <2 x i16*> %vec, i32 0 - store i16* %dummy, i16** undef - ret void - -end: - %vec = load <2 x i16*>, <2 x i16*>* undef - br label %block -} - ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: %2:_(<2 x p0>) = G_INSERT_VECTOR_ELT %0:_, %{{[0-9]+}}:_(p0), %{{[0-9]+}}:_(s32) (in function: vector_of_pointers_insertelement) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_insertelement ; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_insertelement: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir index 0144df5..bc3d049 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir @@ -131,3 +131,20 @@ body: | $x0 = COPY %5(s64) RET_ReallyLR ... +--- +name: test_eve_v2p0 +body: | + bb.0: + liveins: $q0, $q1, $x0 + ; CHECK-LABEL: name: test_eve_v2p0 + ; CHECK: [[COPY:%[0-9]+]]:_(<2 x p0>) = COPY $q0 + ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK: [[EVEC:%[0-9]+]]:_(p0) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x p0>), [[COPY1]](s64) + ; CHECK: $x0 = COPY [[EVEC]](p0) + ; CHECK: RET_ReallyLR + %0:_(<2 x p0>) = COPY $q0 + %2:_(s64) = COPY $x0 + %3:_(p0) = G_EXTRACT_VECTOR_ELT %0:_(<2 x p0>), %2:_(s64) + $x0 = COPY %3(p0) + RET_ReallyLR +... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir index 17cd2ee..919fec7 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=instruction-select %s -o - | FileCheck %s +# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=instruction-select -global-isel-abort=1 %s -o - | FileCheck %s ... --- name: v2s32_fpr @@ -209,3 +209,27 @@ body: | %5:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %4(s64) $h0 = COPY %5(s16) RET_ReallyLR implicit $h0 +... +--- +name: v2p0 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $q0 + + ; CHECK-LABEL: name: v2p0 + ; CHECK: liveins: $q0 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 + ; CHECK: [[CPYi64_:%[0-9]+]]:fpr64 = CPYi64 [[COPY]], 1 + ; CHECK: $d0 = COPY [[CPYi64_]] + ; CHECK: RET_ReallyLR implicit $d0 + %0:fpr(<2 x p0>) = COPY $q0 + %2:gpr(s64) = G_CONSTANT i64 1 + %1:fpr(p0) = G_EXTRACT_VECTOR_ELT %0(<2 x p0>), %2(s64) + $d0 = COPY %1(p0) + RET_ReallyLR implicit $d0 + +... -- 2.7.4