From c567c78f4ed6c03853a48db6a801534655ae58e4 Mon Sep 17 00:00:00 2001 From: Dom Cobley Date: Thu, 7 May 2020 18:16:07 +0100 Subject: [PATCH] vc4_hdmi: Fix up CEC registers Fix an incorrect register address, add a missing one and reorder into address order Signed-off-by: Dom Cobley --- drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h index ea948ff..a0fa082a 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h +++ b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h @@ -33,11 +33,12 @@ enum vc4_hdmi_field { HDMI_CEC_CNTRL_3, HDMI_CEC_CNTRL_4, HDMI_CEC_CNTRL_5, + HDMI_CEC_CPU_STATUS, + HDMI_CEC_CPU_SET, HDMI_CEC_CPU_CLEAR, - HDMI_CEC_CPU_MASK_CLEAR, - HDMI_CEC_CPU_MASK_SET, HDMI_CEC_CPU_MASK_STATUS, - HDMI_CEC_CPU_STATUS, + HDMI_CEC_CPU_MASK_SET, + HDMI_CEC_CPU_MASK_CLEAR, /* * Transmit data, first byte is low byte of the 32-bit reg. @@ -205,9 +206,10 @@ static const struct vc4_hdmi_register vc4_hdmi_fields[] = { VC4_HDMI_REG(HDMI_TX_PHY_RESET_CTL, 0x02c0), VC4_HDMI_REG(HDMI_TX_PHY_CTL_0, 0x02c4), VC4_HDMI_REG(HDMI_CEC_CPU_STATUS, 0x0340), + VC4_HDMI_REG(HDMI_CEC_CPU_SET, 0x0344), VC4_HDMI_REG(HDMI_CEC_CPU_CLEAR, 0x0348), VC4_HDMI_REG(HDMI_CEC_CPU_MASK_STATUS, 0x034c), - VC4_HDMI_REG(HDMI_CEC_CPU_MASK_SET, 0x034c), + VC4_HDMI_REG(HDMI_CEC_CPU_MASK_SET, 0x0350), VC4_HDMI_REG(HDMI_CEC_CPU_MASK_CLEAR, 0x0354), VC4_HDMI_REG(HDMI_RAM_PACKET_START, 0x0400), }; -- 2.7.4