From c54e5c2fb22795bcce1ff18f2a0a70d6a4c647a4 Mon Sep 17 00:00:00 2001 From: Jordan Justen Date: Sun, 17 Apr 2016 13:08:01 -0700 Subject: [PATCH] i965: Use offset instead of index in brw_store_register_mem64 This matches the byte based offset of brw_load_register_mem*. The function is also moved into intel_batchbuffer.c like brw_load_register_mem*. Signed-off-by: Jordan Justen Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_context.h | 4 +- .../drivers/dri/i965/brw_performance_monitor.c | 5 +- src/mesa/drivers/dri/i965/gen6_queryobj.c | 57 ++++------------------ src/mesa/drivers/dri/i965/gen7_sol_state.c | 3 +- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 37 ++++++++++++++ 5 files changed, 52 insertions(+), 54 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 7468dfa..948b082 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -1432,8 +1432,6 @@ void brw_emit_query_end(struct brw_context *brw); void gen6_init_queryobj_functions(struct dd_function_table *functions); void brw_write_timestamp(struct brw_context *brw, drm_intel_bo *bo, int idx); void brw_write_depth_count(struct brw_context *brw, drm_intel_bo *bo, int idx); -void brw_store_register_mem64(struct brw_context *brw, - drm_intel_bo *bo, uint32_t reg, int idx); /** brw_conditional_render.c */ void brw_init_conditional_render_functions(struct dd_function_table *functions); @@ -1450,6 +1448,8 @@ void brw_load_register_mem64(struct brw_context *brw, drm_intel_bo *bo, uint32_t read_domains, uint32_t write_domain, uint32_t offset); +void brw_store_register_mem64(struct brw_context *brw, + drm_intel_bo *bo, uint32_t reg, uint32_t offset); /*====================================================================== * brw_state_dump.c diff --git a/src/mesa/drivers/dri/i965/brw_performance_monitor.c b/src/mesa/drivers/dri/i965/brw_performance_monitor.c index 7e90e8a..a91c6e2 100644 --- a/src/mesa/drivers/dri/i965/brw_performance_monitor.c +++ b/src/mesa/drivers/dri/i965/brw_performance_monitor.c @@ -574,10 +574,9 @@ monitor_needs_statistics_registers(struct brw_context *brw, static void snapshot_statistics_registers(struct brw_context *brw, struct brw_perf_monitor_object *monitor, - uint32_t offset_in_bytes) + uint32_t offset) { struct gl_context *ctx = &brw->ctx; - const int offset = offset_in_bytes / sizeof(uint64_t); const int group = PIPELINE_STATS_COUNTERS; const int num_counters = ctx->PerfMonitor.Groups[group].NumCounters; @@ -590,7 +589,7 @@ snapshot_statistics_registers(struct brw_context *brw, brw_store_register_mem64(brw, monitor->pipeline_stats_bo, brw->perfmon.statistics_registers[i], - offset + i); + offset + i * sizeof(uint64_t)); } } } diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c b/src/mesa/drivers/dri/i965/gen6_queryobj.c index d508c4c..960ccfd 100644 --- a/src/mesa/drivers/dri/i965/gen6_queryobj.c +++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c @@ -39,49 +39,6 @@ #include "intel_batchbuffer.h" #include "intel_reg.h" -/* - * Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM. - * - * Only TIMESTAMP and PS_DEPTH_COUNT have special PIPE_CONTROL support; other - * counters have to be read via the generic MI_STORE_REGISTER_MEM. - * - * Callers must explicitly flush the pipeline to ensure the desired value is - * available. - */ -void -brw_store_register_mem64(struct brw_context *brw, - drm_intel_bo *bo, uint32_t reg, int idx) -{ - assert(brw->gen >= 6); - - /* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to - * read a full 64-bit register, we need to do two of them. - */ - if (brw->gen >= 8) { - BEGIN_BATCH(8); - OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2)); - OUT_BATCH(reg); - OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, - idx * sizeof(uint64_t)); - OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2)); - OUT_BATCH(reg + sizeof(uint32_t)); - OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, - sizeof(uint32_t) + idx * sizeof(uint64_t)); - ADVANCE_BATCH(); - } else { - BEGIN_BATCH(6); - OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2)); - OUT_BATCH(reg); - OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, - idx * sizeof(uint64_t)); - OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2)); - OUT_BATCH(reg + sizeof(uint32_t)); - OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, - sizeof(uint32_t) + idx * sizeof(uint64_t)); - ADVANCE_BATCH(); - } -} - static void write_primitives_generated(struct brw_context *brw, drm_intel_bo *query_bo, int stream, int idx) @@ -90,9 +47,11 @@ write_primitives_generated(struct brw_context *brw, if (brw->gen >= 7 && stream > 0) { brw_store_register_mem64(brw, query_bo, - GEN7_SO_PRIM_STORAGE_NEEDED(stream), idx); + GEN7_SO_PRIM_STORAGE_NEEDED(stream), + idx * sizeof(uint64_t)); } else { - brw_store_register_mem64(brw, query_bo, CL_INVOCATION_COUNT, idx); + brw_store_register_mem64(brw, query_bo, CL_INVOCATION_COUNT, + idx * sizeof(uint64_t)); } } @@ -103,9 +62,11 @@ write_xfb_primitives_written(struct brw_context *brw, brw_emit_mi_flush(brw); if (brw->gen >= 7) { - brw_store_register_mem64(brw, bo, GEN7_SO_NUM_PRIMS_WRITTEN(stream), idx); + brw_store_register_mem64(brw, bo, GEN7_SO_NUM_PRIMS_WRITTEN(stream), + idx * sizeof(uint64_t)); } else { - brw_store_register_mem64(brw, bo, GEN6_SO_NUM_PRIMS_WRITTEN, idx); + brw_store_register_mem64(brw, bo, GEN6_SO_NUM_PRIMS_WRITTEN, + idx * sizeof(uint64_t)); } } @@ -159,7 +120,7 @@ emit_pipeline_stat(struct brw_context *brw, drm_intel_bo *bo, */ brw_emit_mi_flush(brw); - brw_store_register_mem64(brw, bo, reg, idx); + brw_store_register_mem64(brw, bo, reg, idx * sizeof(uint64_t)); } diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c b/src/mesa/drivers/dri/i965/gen7_sol_state.c index dd52c59..d8dbc5f 100644 --- a/src/mesa/drivers/dri/i965/gen7_sol_state.c +++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c @@ -370,9 +370,10 @@ gen7_save_primitives_written_counters(struct brw_context *brw, /* Emit MI_STORE_REGISTER_MEM commands to write the values. */ for (int i = 0; i < streams; i++) { + int offset = (obj->prim_count_buffer_index + i) * sizeof(uint64_t); brw_store_register_mem64(brw, obj->prim_count_bo, GEN7_SO_NUM_PRIMS_WRITTEN(i), - obj->prim_count_buffer_index + i); + offset); } /* Update where to write data to. */ diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index e41f927..cd5d301 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -537,3 +537,40 @@ brw_load_register_mem64(struct brw_context *brw, { load_sized_register_mem(brw, reg, bo, read_domains, write_domain, offset, 2); } + +/* + * Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM. + */ +void +brw_store_register_mem64(struct brw_context *brw, + drm_intel_bo *bo, uint32_t reg, uint32_t offset) +{ + assert(brw->gen >= 6); + + /* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to + * read a full 64-bit register, we need to do two of them. + */ + if (brw->gen >= 8) { + BEGIN_BATCH(8); + OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2)); + OUT_BATCH(reg); + OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, + offset); + OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2)); + OUT_BATCH(reg + sizeof(uint32_t)); + OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, + offset + sizeof(uint32_t)); + ADVANCE_BATCH(); + } else { + BEGIN_BATCH(6); + OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2)); + OUT_BATCH(reg); + OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, + offset); + OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2)); + OUT_BATCH(reg + sizeof(uint32_t)); + OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, + offset + sizeof(uint32_t)); + ADVANCE_BATCH(); + } +} -- 2.7.4