From c54c61cda4fd2c5c4f94e8390b030e8f53a6aaec Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Wed, 15 Nov 2023 14:48:43 +0000 Subject: [PATCH] ARM: dts: Add BCM2712 D0 dts Signed-off-by: Phil Elwell --- arch/arm/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts | 107 +++++++++++++++++++++ arch/arm64/boot/dts/broadcom/Makefile | 1 + arch/arm64/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts | 2 + 3 files changed, 110 insertions(+) create mode 100644 arch/arm/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts diff --git a/arch/arm/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts b/arch/arm/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts new file mode 100644 index 0000000..32aab40 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "bcm2712-rpi-5-b.dts" + +&gio { + brcm,gpio-bank-widths = <32 4>; + + gpio-line-names = + "", // GPIO_000 + "2712_BOOT_CS_N", // GPIO_001 + "2712_BOOT_MISO", // GPIO_002 + "2712_BOOT_MOSI", // GPIO_003 + "2712_BOOT_SCLK", // GPIO_004 + "", // GPIO_005 + "", // GPIO_006 + "", // GPIO_007 + "", // GPIO_008 + "", // GPIO_009 + "", // GPIO_010 + "", // GPIO_011 + "", // GPIO_012 + "", // GPIO_013 + "PCIE_SDA", // GPIO_014 + "PCIE_SCL", // GPIO_015 + "", // GPIO_016 + "", // GPIO_017 + "-", // GPIO_018 + "-", // GPIO_019 + "PWR_GPIO", // GPIO_020 + "2712_G21_FS", // GPIO_021 + "-", // GPIO_022 + "-", // GPIO_023 + "BT_RTS", // GPIO_024 + "BT_CTS", // GPIO_025 + "BT_TXD", // GPIO_026 + "BT_RXD", // GPIO_027 + "WL_ON", // GPIO_028 + "BT_ON", // GPIO_029 + "WIFI_SDIO_CLK", // GPIO_030 + "WIFI_SDIO_CMD", // GPIO_031 + "WIFI_SDIO_D0", // GPIO_032 + "WIFI_SDIO_D1", // GPIO_033 + "WIFI_SDIO_D2", // GPIO_034 + "WIFI_SDIO_D3"; // GPIO_035 +}; + +&gio_aon { + brcm,gpio-bank-widths = <15 6>; + + gpio-line-names = + "RP1_SDA", // AON_GPIO_00 + "RP1_SCL", // AON_GPIO_01 + "RP1_RUN", // AON_GPIO_02 + "SD_IOVDD_SEL", // AON_GPIO_03 + "SD_PWR_ON", // AON_GPIO_04 + "SD_CDET_N", // AON_GPIO_05 + "SD_FLG_N", // AON_GPIO_06 + "", // AON_GPIO_07 + "2712_WAKE", // AON_GPIO_08 + "2712_STAT_LED", // AON_GPIO_09 + "", // AON_GPIO_10 + "", // AON_GPIO_11 + "PMIC_INT", // AON_GPIO_12 + "UART_TX_FS", // AON_GPIO_13 + "UART_RX_FS", // AON_GPIO_14 + "", // AON_GPIO_15 + "", // AON_GPIO_16 + + // Pad bank0 out to 32 entries + "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", + + "HDMI0_SCL", // AON_SGPIO_00 + "HDMI0_SDA", // AON_SGPIO_01 + "HDMI1_SCL", // AON_SGPIO_02 + "HDMI1_SDA", // AON_SGPIO_03 + "PMIC_SCL", // AON_SGPIO_04 + "PMIC_SDA"; // AON_SGPIO_05 +}; + +&pinctrl { + compatible = "brcm,bcm2712d0-pinctrl"; + reg = <0x7d504100 0x20>; +}; + +&pinctrl_aon { + compatible = "brcm,bcm2712d0-aon-pinctrl"; + reg = <0x7d510700 0x1c>; +}; + +&vc4 { + compatible = "brcm,bcm2712d0-vc6"; +}; + +&uart10 { + interrupts = ; +}; + +&spi10 { + dmas = <&dma40 3>, <&dma40 4>; +}; + +&hdmi0 { + dmas = <&dma40 (12|(1<<30)|(1<<24)|(10<<16)|(15<<20))>; +}; + +&hdmi1 { + dmas = <&dma40 (13|(1<<30)|(1<<24)|(10<<16)|(15<<20))>; +}; diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile index 0c75985..273ee18 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -21,6 +21,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-cm3.dtb dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-cm4.dtb dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-cm4s.dtb dtb-$(CONFIG_ARCH_BCM2835) += bcm2712-rpi-5-b.dtb +dtb-$(CONFIG_ARCH_BCM2835) += bcm2712d0-rpi-5-b.dtb subdir-y += bcmbca subdir-y += northstar2 diff --git a/arch/arm64/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts new file mode 100644 index 0000000..9b3ddbb --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "../../../../arm/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts" -- 2.7.4