From c53c2591f607409e311a2b319d95d17ea336a836 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Tue, 11 Aug 2009 19:05:38 +0200 Subject: [PATCH] re PR target/8603 ([Alpha] s?addl pattern doesn't work) PR target/8603 * config/alpha/alpha.md (addsi3): Remove expander. (addsi3): Rename from *addsi3_internal insn pattern. (subsi3): Remove expander. (subsi3): Rename from *subsi3_internal insn pattern. From-SVN: r150654 --- gcc/ChangeLog | 33 +++++++++++++++++++-------------- gcc/config/alpha/alpha.md | 20 ++------------------ 2 files changed, 21 insertions(+), 32 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6f414a0..8acb3b6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,11 +1,19 @@ +2009-08-11 Uros Bizjak + + PR target/8603 + * config/alpha/alpha.md (addsi3): Remove expander. + (addsi3): Rename from *addsi3_internal insn pattern. + (subsi3): Remove expander. + (subsi3): Rename from *subsi3_internal insn pattern. + 2009-08-11 Douglas B Rupp * config/alpha/alpha.c (alpha_init_builtins): Nullify FWRITE and FWRITE_UNLOCKED. 2009-08-11 Vasiliy Fofanov - Eric Botcazou - Douglas B Rupp + Eric Botcazou + Douglas B Rupp * config/alpha/alpha.c (alpha_return_in_memory): On VMS, ensure that records that fit in 64 bits are returned by immediate value, @@ -22,10 +30,9 @@ not valid in the outer mode. 2009-08-11 Richard Guenther - - PR bootstrap/40788 - * builtins.c (gimplify_va_arg_expr): Do not call - SET_EXPR_LOCATION. + + PR bootstrap/40788 + * builtins.c (gimplify_va_arg_expr): Do not call SET_EXPR_LOCATION. 2009-08-10 Douglas B Rupp @@ -33,7 +40,7 @@ (OVERRIDE_OPTIONS): Incorporate removed OPTIMIZATION_OPTIONS. 2009-08-10 Olivier Hainque - Douglas B Rupp + Douglas B Rupp * config/alpha/alpha.c (alpha_sa_size): Force procedure type to PT_STACK when frame_pointer_needed on OpenVMS. @@ -52,7 +59,7 @@ Call alpha_vms_can_eliminate and alpha_vms_initial_elimination_offset. 2009-08-10 Eric Botcazou - Douglas B Rupp + Douglas B Rupp * config/alpha/alpha.c (common_object_handler): New function. (vms_attribute_table): Declare a single attribute "common_object". @@ -116,7 +123,7 @@ doc/invoke.texi (mmalloc64): Document switch. 2009-08-09 Olivier Hainque - Douglas B Rupp + Douglas B Rupp * config/alpha/alpha.c (struct machine_function): New flag for VMS, uses_condition_handler. @@ -145,7 +152,7 @@ * config/alpha/vms.h (MD_UNWIND_SUPPORT): 2009-08-09 Eric Botcazou - Douglas B Rupp + Douglas B Rupp * config/alpha/alpha.c (alpha_links): Add 'target' field. (alpha_need_linkage): Handle aliases. Return function symbol. @@ -203,8 +210,7 @@ 2009-08-09 Richard Guenther PR tree-optimization/41016 - * tree-ssa-ifcombine.c (get_name_for_bit_test): Fix tuplification - bug. + * tree-ssa-ifcombine.c (get_name_for_bit_test): Fix tuplification bug. (operand_precision): Remove. (integral_operand_p): Likewise. (recognize_single_bit_test): Adjust. @@ -252,8 +258,7 @@ (force_expr_to_var_cost): Cast target_spill_cost to int. (get_address_cost): New arguments STMT_AFTER_INC and MAY_AUTOINC. All callers changed. Check for availability of autoinc addressing - modes, both in general for a given mode, and in the specific use - case. + modes, both in general for a given mode, and in the specific use case. (get_computation_cost_at): New argument CAN_AUTOINC. All callers changed. (get_computation_cost): Likewise. diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 935cc94..18817c8 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -256,16 +256,7 @@ (sign_extend:DI (match_dup 1)))] "") -;; Don't say we have addsi3 if optimizing. This generates better code. We -;; have the anonymous addsi3 pattern below in case combine wants to make it. -(define_expand "addsi3" - [(set (match_operand:SI 0 "register_operand" "") - (plus:SI (match_operand:SI 1 "reg_or_0_operand" "") - (match_operand:SI 2 "add_operand" "")))] - "! optimize" - "") - -(define_insn "*addsi_internal" +(define_insn "addsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ") (match_operand:SI 2 "add_operand" "rI,O,K,L")))] @@ -619,14 +610,7 @@ "" "subqv $31,%1,%0") -(define_expand "subsi3" - [(set (match_operand:SI 0 "register_operand" "") - (minus:SI (match_operand:SI 1 "reg_or_0_operand" "") - (match_operand:SI 2 "reg_or_8bit_operand" "")))] - "! optimize" - "") - -(define_insn "*subsi_internal" +(define_insn "subsi3" [(set (match_operand:SI 0 "register_operand" "=r") (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") (match_operand:SI 2 "reg_or_8bit_operand" "rI")))] -- 2.7.4