From c5368505265c0ed5551ce5d90bf3d383015e7cdf Mon Sep 17 00:00:00 2001 From: Marek Olsak Date: Thu, 15 Jan 2015 18:43:01 +0000 Subject: [PATCH] R600/SI: Use 64-bit encoding by default for opcodes that are VOP3-only on VI llvm-svn: 226190 --- llvm/lib/Target/R600/SIInstrInfo.cpp | 6 ++-- llvm/lib/Target/R600/SIInstructions.td | 2 +- llvm/test/CodeGen/R600/ctpop.ll | 66 +++++++++++++++++----------------- llvm/test/CodeGen/R600/ctpop64.ll | 3 +- 4 files changed, 37 insertions(+), 40 deletions(-) diff --git a/llvm/lib/Target/R600/SIInstrInfo.cpp b/llvm/lib/Target/R600/SIInstrInfo.cpp index 6de4fa3..b2c6ac6 100644 --- a/llvm/lib/Target/R600/SIInstrInfo.cpp +++ b/llvm/lib/Target/R600/SIInstrInfo.cpp @@ -615,7 +615,7 @@ unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB, .addImm(-1) .addImm(0); - BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e32), + BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64), TIDReg) .addImm(-1) .addReg(TIDReg); @@ -1291,7 +1291,7 @@ unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) { case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64; case AMDGPU::S_LOAD_DWORDX4_IMM: case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64; - case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e32; + case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64; case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32; case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32; } @@ -2282,7 +2282,7 @@ void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl &Worklist MachineOperand &Dest = Inst->getOperand(0); MachineOperand &Src = Inst->getOperand(1); - const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e32); + const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64); const TargetRegisterClass *SrcRC = Src.isReg() ? MRI.getRegClass(Src.getReg()) : &AMDGPU::SGPR_32RegClass; diff --git a/llvm/lib/Target/R600/SIInstructions.td b/llvm/lib/Target/R600/SIInstructions.td index c5c9306..8fdacac 100644 --- a/llvm/lib/Target/R600/SIInstructions.td +++ b/llvm/lib/Target/R600/SIInstructions.td @@ -2735,7 +2735,7 @@ let Predicates = [isSICI] in { def : Pat < (int_SI_tid), - (V_MBCNT_HI_U32_B32_e32 0xffffffff, + (V_MBCNT_HI_U32_B32_e64 0xffffffff, (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0)) >; diff --git a/llvm/test/CodeGen/R600/ctpop.ll b/llvm/test/CodeGen/R600/ctpop.ll index a47bc87..c64f443 100644 --- a/llvm/test/CodeGen/R600/ctpop.ll +++ b/llvm/test/CodeGen/R600/ctpop.ll @@ -24,8 +24,7 @@ define void @s_ctpop_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind { ; XXX - Why 0 in register? ; FUNC-LABEL: {{^}}v_ctpop_i32: ; SI: buffer_load_dword [[VAL:v[0-9]+]], -; SI: v_mov_b32_e32 [[VZERO:v[0-9]+]], 0 -; SI: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], [[VAL]], [[VZERO]] +; SI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 0 ; SI: buffer_store_dword [[RESULT]], ; SI: s_endpgm @@ -40,8 +39,7 @@ define void @v_ctpop_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noali ; FUNC-LABEL: {{^}}v_ctpop_add_chain_i32: ; SI: buffer_load_dword [[VAL0:v[0-9]+]], ; SI: buffer_load_dword [[VAL1:v[0-9]+]], -; SI: v_mov_b32_e32 [[VZERO:v[0-9]+]], 0 -; SI: v_bcnt_u32_b32_e32 [[MIDRESULT:v[0-9]+]], [[VAL1]], [[VZERO]] +; SI: v_bcnt_u32_b32_e64 [[MIDRESULT:v[0-9]+]], [[VAL1]], 0 ; SI-NEXT: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], [[VAL0]], [[MIDRESULT]] ; SI: buffer_store_dword [[RESULT]], ; SI: s_endpgm @@ -73,8 +71,8 @@ define void @v_ctpop_add_sgpr_i32(i32 addrspace(1)* noalias %out, i32 addrspace( } ; FUNC-LABEL: {{^}}v_ctpop_v2i32: -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 ; SI: s_endpgm ; EG: BCNT_INT @@ -87,10 +85,10 @@ define void @v_ctpop_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrs } ; FUNC-LABEL: {{^}}v_ctpop_v4i32: -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 ; SI: s_endpgm ; EG: BCNT_INT @@ -105,14 +103,14 @@ define void @v_ctpop_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrs } ; FUNC-LABEL: {{^}}v_ctpop_v8i32: -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 ; SI: s_endpgm ; EG: BCNT_INT @@ -131,22 +129,22 @@ define void @v_ctpop_v8i32(<8 x i32> addrspace(1)* noalias %out, <8 x i32> addrs } ; FUNC-LABEL: {{^}}v_ctpop_v16i32: -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 -; SI: v_bcnt_u32_b32_e32 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 +; SI: v_bcnt_u32_b32_e64 ; SI: s_endpgm ; EG: BCNT_INT diff --git a/llvm/test/CodeGen/R600/ctpop64.ll b/llvm/test/CodeGen/R600/ctpop64.ll index 8dfe571..9758ac9 100644 --- a/llvm/test/CodeGen/R600/ctpop64.ll +++ b/llvm/test/CodeGen/R600/ctpop64.ll @@ -21,8 +21,7 @@ define void @s_ctpop_i64(i32 addrspace(1)* noalias %out, i64 %val) nounwind { ; FUNC-LABEL: {{^}}v_ctpop_i64: ; SI: buffer_load_dwordx2 v{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}}, -; SI: v_mov_b32_e32 [[VZERO:v[0-9]+]], 0 -; SI: v_bcnt_u32_b32_e32 [[MIDRESULT:v[0-9]+]], v[[LOVAL]], [[VZERO]] +; SI: v_bcnt_u32_b32_e64 [[MIDRESULT:v[0-9]+]], v[[LOVAL]], 0 ; SI-NEXT: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]] ; SI: buffer_store_dword [[RESULT]], ; SI: s_endpgm -- 2.7.4