From c4e00289a78116aefc8db41979d747ab27c4bd44 Mon Sep 17 00:00:00 2001 From: Saleem Abdulrasool Date: Sat, 19 Jul 2014 01:29:51 +0000 Subject: [PATCH] ARM: correct WoA __builtin_alloca handling on O0 When performing a dynamic stack adjustment without optimisations, we would mark SP as def and R4 as kill. This occurred as part of the expansion of a WIN__CHKSTK SDNode which indicated the proper handling of SP and R4. The result would be that we would double define SP as part of an operation, which is obviously incorrect. Furthermore, the VTList for the chain had an incorrect parameter type of i32 instead of Other. Correct these to permit proper lowering of __builtin_alloca at -O0. llvm-svn: 213442 --- llvm/lib/Target/ARM/ARMISelLowering.cpp | 5 ++--- llvm/test/CodeGen/ARM/Windows/alloca.ll | 22 ++++++++++++++++++++++ 2 files changed, 24 insertions(+), 3 deletions(-) create mode 100644 llvm/test/CodeGen/ARM/Windows/alloca.ll diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index f6f937a..5c14ed6 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -7227,8 +7227,7 @@ ARMTargetLowering::EmitLowered__chkstk(MachineInstr *MI, AddDefaultCC(AddDefaultPred(BuildMI(*MBB, MI, DL, TII.get(ARM::t2SUBrr), ARM::SP) - .addReg(ARM::SP, RegState::Define) - .addReg(ARM::R4, RegState::Kill))); + .addReg(ARM::SP).addReg(ARM::R4))); MI->eraseFromParent(); return MBB; @@ -10622,7 +10621,7 @@ ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const Chain = DAG.getCopyToReg(Chain, DL, ARM::R4, Words, Flag); Flag = Chain.getValue(1); - SDVTList NodeTys = DAG.getVTList(MVT::i32, MVT::Glue); + SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); Chain = DAG.getNode(ARMISD::WIN__CHKSTK, DL, NodeTys, Chain, Flag); SDValue NewSP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32); diff --git a/llvm/test/CodeGen/ARM/Windows/alloca.ll b/llvm/test/CodeGen/ARM/Windows/alloca.ll new file mode 100644 index 0000000..6a3d002 --- /dev/null +++ b/llvm/test/CodeGen/ARM/Windows/alloca.ll @@ -0,0 +1,22 @@ +; RUN: llc -O0 -mtriple thumbv7-windows-itanium -filetype asm -o - %s | FileCheck %s + +declare arm_aapcs_vfpcc i32 @num_entries() + +define arm_aapcs_vfpcc void @test___builtin_alloca() { +entry: + %array = alloca i8*, align 4 + %call = call arm_aapcs_vfpcc i32 @num_entries() + %mul = mul i32 4, %call + %0 = alloca i8, i32 %mul + store i8* %0, i8** %array, align 4 + ret void +} + +; CHECK: bl num_entries +; CHECK: movs [[R1:r[0-9]+]], #7 +; CHECK: add.w [[R0:r[0-9]+]], [[R1]], [[R0]], lsl #2 +; CHECK: bic [[R0]], [[R0]], #7 +; CHECK: lsrs r4, [[R0]], #2 +; CHECK: bl __chkstk +; CHECK: sub.w sp, sp, r4 + -- 2.7.4