From c4ab1bdcc9710e3c7cc7115d3be9c69b7e7712ef Mon Sep 17 00:00:00 2001 From: Neil Roberts Date: Tue, 24 Apr 2018 12:17:56 +0200 Subject: [PATCH] =?utf8?q?spirv:=20Don=E2=80=99t=20check=20for=20NaN=20for?= =?utf8?q?=20most=20OpFOrd*=20comparisons?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit For all of the OpFOrd* comparisons except OpFOrdNotEqual the hardware should probably already return false if one of the operands is NaN so we don’t need to have an explicit check for it. This seems to at least work on Intel hardware. This should reduce the number of instructions generated for the most common comparisons. For what it’s worth, the original code to handle this was added in e062eb6415de3a. The commit message for that says that it was to fix some CTS tests for OpFUnord* opcodes. Even if the hardware doesn’t handle NaNs this patch shouldn’t affect those tests. At any rate they have since been moved out of the mustpass list. Incidentally those tests fail on the nvidia proprietary driver so it doesn’t seem like handling NaNs correctly is a priority. Reviewed-by: Iago Toral Quiroga Reviewed-by: Bas Nieuwenhuizen --- src/compiler/spirv/vtn_alu.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c index 71e743c..3134849 100644 --- a/src/compiler/spirv/vtn_alu.c +++ b/src/compiler/spirv/vtn_alu.c @@ -597,23 +597,18 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode, break; } - case SpvOpFOrdEqual: - case SpvOpFOrdNotEqual: - case SpvOpFOrdLessThan: - case SpvOpFOrdGreaterThan: - case SpvOpFOrdLessThanEqual: - case SpvOpFOrdGreaterThanEqual: { + case SpvOpFOrdNotEqual: { + /* For all the SpvOpFOrd* comparisons apart from NotEqual, the value + * from the ALU will probably already be false if the operands are not + * ordered so we don’t need to handle it specially. + */ bool swap; unsigned src_bit_size = glsl_get_bit_size(vtn_src[0]->type); unsigned dst_bit_size = glsl_get_bit_size(type); nir_op op = vtn_nir_alu_op_for_spirv_opcode(b, opcode, &swap, src_bit_size, dst_bit_size); - if (swap) { - nir_ssa_def *tmp = src[0]; - src[0] = src[1]; - src[1] = tmp; - } + assert(!swap); val->ssa->def = nir_iand(&b->nb, -- 2.7.4