From c49428a97daa28c4ba404140af8ffa2ffbf81a62 Mon Sep 17 00:00:00 2001 From: Jessica Paquette Date: Mon, 28 Jan 2019 19:53:14 +0000 Subject: [PATCH] [GlobalISel][AArch64] Add instruction selection support for @llvm.log10 This adds instruction selection support for @llvm.log10 in AArch64. It teaches GISel to lower it to a library call, updates the relevant tests, and adds a legalizer test for log10. https://reviews.llvm.org/D57341 llvm-svn: 352418 --- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 8 +- llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp | 2 +- .../lib/Target/AArch64/AArch64RegisterBankInfo.cpp | 1 + .../CodeGen/AArch64/GlobalISel/legalize-log10.mir | 227 +++++++++++++++++++++ .../GlobalISel/legalizer-info-validation.mir | 2 +- .../test/CodeGen/AArch64/arm64-vfloatintrinsics.ll | 19 ++ llvm/test/CodeGen/AArch64/f16-instructions.ll | 13 ++ 7 files changed, 269 insertions(+), 3 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/legalize-log10.mir diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index 60f8168..4c686a5 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -130,6 +130,10 @@ static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) { assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size"); return Size == 128 ? RTLIB::COS_F128 : Size == 64 ? RTLIB::COS_F64 : RTLIB::COS_F32; + case TargetOpcode::G_FLOG10: + assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size"); + return Size == 128 ? RTLIB::LOG10_F128 + : Size == 64 ? RTLIB::LOG10_F64 : RTLIB::LOG10_F32; } llvm_unreachable("Unknown libcall function"); } @@ -223,7 +227,8 @@ LegalizerHelper::libcall(MachineInstr &MI) { case TargetOpcode::G_FPOW: case TargetOpcode::G_FREM: case TargetOpcode::G_FCOS: - case TargetOpcode::G_FSIN: { + case TargetOpcode::G_FSIN: + case TargetOpcode::G_FLOG10: { if (Size > 64) { LLVM_DEBUG(dbgs() << "Size " << Size << " too large to legalize.\n"); return UnableToLegalize; @@ -1084,6 +1089,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) { case TargetOpcode::G_FCEIL: case TargetOpcode::G_FCOS: case TargetOpcode::G_FSIN: + case TargetOpcode::G_FLOG10: assert(TypeIdx == 0); Observer.changingInstr(MI); diff --git a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp index b42c675..e2c6fca 100644 --- a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp @@ -143,7 +143,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) { [=](const LegalityQuery &Query) { return std::make_pair(0, s32); }) .legalFor({s16, s32, s64, v2s32, v4s32, v2s64, v2s16, v4s16, v8s16}); - getActionDefinitionsBuilder({G_FCOS, G_FSIN}) + getActionDefinitionsBuilder({G_FCOS, G_FSIN, G_FLOG10}) // We need a call for these, so we always need to scalarize. .scalarize(0) // Regardless of FP16 support, widen 16-bit elements to 32-bits. diff --git a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp index e352bbc..5642278 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp @@ -395,6 +395,7 @@ static bool isPreISelGenericFloatingPointOpcode(unsigned Opc) { case TargetOpcode::G_FNEG: case TargetOpcode::G_FCOS: case TargetOpcode::G_FSIN: + case TargetOpcode::G_FLOG10: return true; } return false; diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log10.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log10.mir new file mode 100644 index 0000000..08e1a4f --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log10.mir @@ -0,0 +1,227 @@ +# RUN: llc -verify-machineinstrs -mtriple aarch64--- \ +# RUN: -run-pass=legalizer -mattr=+fullfp16 -global-isel %s -o - \ +# RUN: | FileCheck %s +... +--- +name: test_v4f16.log10 +alignment: 2 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0: + liveins: $d0 + ; CHECK-LABEL: name: test_v4f16.log10 + ; CHECK: [[V1:%[0-9]+]]:_(s16), [[V2:%[0-9]+]]:_(s16), [[V3:%[0-9]+]]:_(s16), [[V4:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s16>) + + ; CHECK-DAG: [[V1_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V1]](s16) + ; CHECK-NEXT: ADJCALLSTACKDOWN + ; CHECK-NEXT: $s0 = COPY [[V1_S32]](s32) + ; CHECK-NEXT: BL &log10 + ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK-NEXT: ADJCALLSTACKUP + ; CHECK-NEXT: [[ELT1:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT1_S32]](s32) + + ; CHECK-DAG: [[V2_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V2]](s16) + ; CHECK-NEXT: ADJCALLSTACKDOWN + ; CHECK-NEXT: $s0 = COPY [[V2_S32]](s32) + ; CHECK-NEXT: BL &log10 + ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK-NEXT: ADJCALLSTACKUP + ; CHECK-NEXT: [[ELT2:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT2_S32]](s32) + + ; CHECK-DAG: [[V3_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V3]](s16) + ; CHECK-NEXT: ADJCALLSTACKDOWN + ; CHECK-NEXT: $s0 = COPY [[V3_S32]](s32) + ; CHECK-NEXT: BL &log10 + ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK-NEXT: ADJCALLSTACKUP + ; CHECK-NEXT: [[ELT3:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT3_S32]](s32) + + ; CHECK-DAG: [[V4_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V4]](s16) + ; CHECK-NEXT: ADJCALLSTACKDOWN + ; CHECK-NEXT: $s0 = COPY [[V4_S32]](s32) + ; CHECK-NEXT: BL &log10 + ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK-NEXT: ADJCALLSTACKUP + ; CHECK-NEXT: [[ELT4:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT4_S32]](s32) + + ; CHECK-DAG: %{{[0-9]+}}:_(<4 x s16>) = G_BUILD_VECTOR [[ELT1]](s16), [[ELT2]](s16), [[ELT3]](s16), [[ELT4]](s16) + + %0:_(<4 x s16>) = COPY $d0 + %1:_(<4 x s16>) = G_FLOG10 %0 + $d0 = COPY %1(<4 x s16>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_v8f16.log10 +alignment: 2 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0: + liveins: $q0 + + ; CHECK-LABEL: name: test_v8f16.log10 + + ; This is big, so let's just check for the 8 calls to log10, the the + ; G_UNMERGE_VALUES, and the G_BUILD_VECTOR. The other instructions ought + ; to be covered by the other tests. + + ; CHECK: G_UNMERGE_VALUES + ; CHECK: BL &log10 + ; CHECK: BL &log10 + ; CHECK: BL &log10 + ; CHECK: BL &log10 + ; CHECK: BL &log10 + ; CHECK: BL &log10 + ; CHECK: BL &log10 + ; CHECK: BL &log10 + ; CHECK-DAG: G_BUILD_VECTOR + + %0:_(<8 x s16>) = COPY $q0 + %1:_(<8 x s16>) = G_FLOG10 %0 + $q0 = COPY %1(<8 x s16>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_v2f32.log10 +alignment: 2 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0: + liveins: $d0 + + ; CHECK-LABEL: name: test_v2f32.log10 + ; CHECK: [[V1:%[0-9]+]]:_(s32), [[V2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %{{[0-9]+}}(<2 x s32>) + + ; CHECK-NEXT: ADJCALLSTACKDOWN + ; CHECK-DAG: $s0 = COPY [[V1]](s32) + ; CHECK-DAG: BL &log10 + ; CHECK-DAG: [[ELT1:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK-DAG: ADJCALLSTACKUP + + ; CHECK-DAG: ADJCALLSTACKDOWN + ; CHECK-DAG: $s0 = COPY [[V2]](s32) + ; CHECK-DAG: BL &log10 + ; CHECK-DAG: [[ELT2:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK-DAG: ADJCALLSTACKUP + + ; CHECK-DAG: %1:_(<2 x s32>) = G_BUILD_VECTOR [[ELT1]](s32), [[ELT2]](s32) + + %0:_(<2 x s32>) = COPY $d0 + %1:_(<2 x s32>) = G_FLOG10 %0 + $d0 = COPY %1(<2 x s32>) + RET_ReallyLR implicit $d0 + +... +--- +name: test_v4f32.log10 +alignment: 2 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0: + liveins: $q0 + ; CHECK-LABEL: name: test_v4f32.log10 + ; CHECK: [[V1:%[0-9]+]]:_(s32), [[V2:%[0-9]+]]:_(s32), [[V3:%[0-9]+]]:_(s32), [[V4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %{{[0-9]+}}(<4 x s32>) + + ; CHECK-NEXT: ADJCALLSTACKDOWN + ; CHECK-DAG: $s0 = COPY [[V1]](s32) + ; CHECK-DAG: BL &log10 + ; CHECK-DAG: [[ELT1:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK-DAG: ADJCALLSTACKUP + + ; CHECK-DAG: ADJCALLSTACKDOWN + ; CHECK-DAG: $s0 = COPY [[V2]](s32) + ; CHECK-DAG: BL &log10 + ; CHECK-DAG: [[ELT2:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK-DAG: ADJCALLSTACKUP + + ; CHECK-DAG: ADJCALLSTACKDOWN + ; CHECK-DAG: $s0 = COPY [[V3]](s32) + ; CHECK-DAG: BL &log10 + ; CHECK-DAG: [[ELT3:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK-DAG: ADJCALLSTACKUP + + ; CHECK-DAG: ADJCALLSTACKDOWN + ; CHECK-DAG: $s0 = COPY [[V4]](s32) + ; CHECK-DAG: BL &log10 + ; CHECK-DAG: [[ELT4:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK-DAG: ADJCALLSTACKUP + + ; CHECK-DAG: %1:_(<4 x s32>) = G_BUILD_VECTOR [[ELT1]](s32), [[ELT2]](s32), [[ELT3]](s32), [[ELT4]](s32) + + %0:_(<4 x s32>) = COPY $q0 + %1:_(<4 x s32>) = G_FLOG10 %0 + $q0 = COPY %1(<4 x s32>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_v2f64.log10 +alignment: 2 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0: + liveins: $q0 + + ; CHECK-LABEL: name: test_v2f64.log10 + ; CHECK: [[V1:%[0-9]+]]:_(s64), [[V2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %{{[0-9]+}}(<2 x s64>) + + ; CHECK-NEXT: ADJCALLSTACKDOWN + ; CHECK-DAG: $d0 = COPY [[V1]](s64) + ; CHECK-DAG: BL &log10 + ; CHECK-DAG: [[ELT1:%[0-9]+]]:_(s64) = COPY $d0 + ; CHECK-DAG: ADJCALLSTACKUP + + ; CHECK-DAG: ADJCALLSTACKDOWN + ; CHECK-DAG: $d0 = COPY [[V2]](s64) + ; CHECK-DAG: BL &log10 + ; CHECK-DAG: [[ELT2:%[0-9]+]]:_(s64) = COPY $d0 + ; CHECK-DAG: ADJCALLSTACKUP + + ; CHECK-DAG: %1:_(<2 x s64>) = G_BUILD_VECTOR [[ELT1]](s64), [[ELT2]](s64) + + %0:_(<2 x s64>) = COPY $q0 + %1:_(<2 x s64>) = G_FLOG10 %0 + $q0 = COPY %1(<2 x s64>) + RET_ReallyLR implicit $q0 + +... +--- +name: test_log10_half +alignment: 2 +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0: + liveins: $h0 + ; CHECK-LABEL: name: test_log10_half + ; CHECK: [[REG1:%[0-9]+]]:_(s32) = G_FPEXT %0(s16) + ; CHECK-NEXT: ADJCALLSTACKDOWN + ; CHECK-NEXT: $s0 = COPY [[REG1]](s32) + ; CHECK-NEXT: BL &log10 + ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0 + ; CHECK-NEXT: ADJCALLSTACKUP + ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s16) = G_FPTRUNC [[REG2]](s32) + + %0:_(s16) = COPY $h0 + %1:_(s16) = G_FLOG10 %0 + $h0 = COPY %1(s16) + RET_ReallyLR implicit $h0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir index 0074daa..ca6df1f 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir @@ -268,7 +268,7 @@ # DEBUG: .. type index coverage check SKIPPED: no rules defined # # DEBUG-NEXT: G_FLOG10 (opcode {{[0-9]+}}): 1 type index -# DEBUG: .. type index coverage check SKIPPED: no rules defined +# DEBUG: .. the first uncovered type index: 1, OK # # DEBUG-NEXT: G_FNEG (opcode {{[0-9]+}}): 1 type index # DEBUG: .. the first uncovered type index: 1, OK diff --git a/llvm/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll b/llvm/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll index 03d1f37..2f5a37a 100644 --- a/llvm/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll +++ b/llvm/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll @@ -80,10 +80,14 @@ define %v4f16 @test_v4f16.log(%v4f16 %a) { %1 = call %v4f16 @llvm.log.v4f16(%v4f16 %a) ret %v4f16 %1 } + +; FALLBACK-NOT: remark{{.*}}test_v4f16.log10 define %v4f16 @test_v4f16.log10(%v4f16 %a) { ; This operation is expanded, whether with or without +fullfp16. ; CHECK-LABEL: test_v4f16.log10: ; CHECK-COUNT-4: bl log10 + ; GISEL-LABEL: test_v4f16.log10: + ; GISEL-COUNT-4: bl log10 %1 = call %v4f16 @llvm.log10.v4f16(%v4f16 %a) ret %v4f16 %1 } @@ -251,10 +255,14 @@ define %v8f16 @test_v8f16.log(%v8f16 %a) { %1 = call %v8f16 @llvm.log.v8f16(%v8f16 %a) ret %v8f16 %1 } + +; FALLBACK-NOT: remark{{.*}}test_v8f16.log10 define %v8f16 @test_v8f16.log10(%v8f16 %a) { ; This operation is expanded, whether with or without +fullfp16. ; CHECK-LABEL: test_v8f16.log10: ; CHECK-COUNT-8: bl log10 + ; GISEL-LABEL: test_v8f16.log10: + ; GISEL-COUNT-8: bl log10 %1 = call %v8f16 @llvm.log10.v8f16(%v8f16 %a) ret %v8f16 %1 } @@ -410,9 +418,13 @@ define %v2f32 @test_v2f32.log(%v2f32 %a) { %1 = call %v2f32 @llvm.log.v2f32(%v2f32 %a) ret %v2f32 %1 } + +; FALLBACK-NOT: remark{{.*}}test_v2f32.log10 ; CHECK: test_v2f32.log10: +; GISEL: test_v2f32.log10: define %v2f32 @test_v2f32.log10(%v2f32 %a) { ; CHECK: log + ; GISEL: log %1 = call %v2f32 @llvm.log10.v2f32(%v2f32 %a) ret %v2f32 %1 } @@ -544,9 +556,12 @@ define %v4f32 @test_v4f32.log(%v4f32 %a) { %1 = call %v4f32 @llvm.log.v4f32(%v4f32 %a) ret %v4f32 %1 } + +; FALLBACK-NOT: remark{{.*}}test_v4f32.log10 ; CHECK: test_v4f32.log10: define %v4f32 @test_v4f32.log10(%v4f32 %a) { ; CHECK: log + ; GISEL: log %1 = call %v4f32 @llvm.log10.v4f32(%v4f32 %a) ret %v4f32 %1 } @@ -677,9 +692,13 @@ define %v2f64 @test_v2f64.log(%v2f64 %a) { %1 = call %v2f64 @llvm.log.v2f64(%v2f64 %a) ret %v2f64 %1 } + +; FALLBACK-NOT: remark{{.*}}test_v2f64.log10 ; CHECK: test_v2f64.log10: +; GISEL: test_v2f64.log10: define %v2f64 @test_v2f64.log10(%v2f64 %a) { ; CHECK: log + ; GISEL: log %1 = call %v2f64 @llvm.log10.v2f64(%v2f64 %a) ret %v2f64 %1 } diff --git a/llvm/test/CodeGen/AArch64/f16-instructions.ll b/llvm/test/CodeGen/AArch64/f16-instructions.ll index df673aa6..2290ced 100644 --- a/llvm/test/CodeGen/AArch64/f16-instructions.ll +++ b/llvm/test/CodeGen/AArch64/f16-instructions.ll @@ -912,6 +912,9 @@ define half @test_log(half %a) #0 { ret half %r } +; FALLBACK-NOT: remark:{{.*}}test_log10 +; FALLBACK-FP16-NOT: remark:{{.*}}test_log10 + ; CHECK-COMMON-LABEL: test_log10: ; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]! ; CHECK-COMMON-NEXT: mov x29, sp @@ -920,6 +923,16 @@ define half @test_log(half %a) #0 { ; CHECK-COMMON-NEXT: fcvt h0, s0 ; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16 ; CHECK-COMMON-NEXT: ret + +; GISEL-LABEL: test_log10: +; GISEL-NEXT: stp x29, x30, [sp, #-16]! +; GISEL-NEXT: mov x29, sp +; GISEL-NEXT: fcvt s0, h0 +; GISEL-NEXT: bl {{_?}}log10f +; GISEL-NEXT: fcvt h0, s0 +; GISEL-NEXT: ldp x29, x30, [sp], #16 +; GISEL-NEXT: ret + define half @test_log10(half %a) #0 { %r = call half @llvm.log10.f16(half %a) ret half %r -- 2.7.4