From c48e0c533e72ca264ac914addccab8a328806ed3 Mon Sep 17 00:00:00 2001 From: Wan Ahmad Zainie Date: Tue, 5 May 2020 21:06:17 +0800 Subject: [PATCH] spi: dw-apb-ssi: Add Intel Keem Bay support Document Intel Keem Bay SPI controller DT bindings. Signed-off-by: Wan Ahmad Zainie Link: https://lore.kernel.org/r/20200505130618.554-7-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt index 2ead46b..7a4702e 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt @@ -2,7 +2,8 @@ Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface. Required properties: - compatible : "snps,dw-apb-ssi" or "mscc,-spi", where soc is "ocelot" or - "jaguar2", or "amazon,alpine-dw-apb-ssi", or "snps,dwc-ssi-1.01a" + "jaguar2", or "amazon,alpine-dw-apb-ssi", or "snps,dwc-ssi-1.01a" or + "intel,keembay-ssi" - reg : The register base for the controller. For "mscc,-spi", a second register set is required (named ICPU_CFG:SPI_MST) - interrupts : One interrupt, used by the controller. -- 2.7.4