From c45a9752f15bbc37d8efda0e29af5a2bfd53729d Mon Sep 17 00:00:00 2001 From: liuhongt Date: Mon, 6 Jun 2022 13:39:19 +0800 Subject: [PATCH] Fix insn does not satisfy its constraints: sse2_lshrv1ti3 21114(define_insn_and_split "ssse3_palignrdi" 21115 [(set (match_operand:DI 0 "register_operand" "=y,x,Yv") 21116 (unspec:DI [(match_operand:DI 1 "register_operand" "0,0,Yv") 21117 (match_operand:DI 2 "register_mmxmem_operand" "ym,x,Yv") 21118 (match_operand:SI 3 "const_0_to_255_mul_8_operand")] 21119 UNSPEC_PALIGNR))] 21120 "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3" Alternative 2 requires Yw instead of Yv since it's splitted to vpsrldq which requires AVX512VL & AVX512BW for evex version. gcc/ChangeLog: PR target/105854 * config/i386/sse.md (ssse3_palignrdi): Change alternative 2 from Yv to Yw. --- gcc/config/i386/sse.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 5e93aa2..3a3ea60 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -20874,9 +20874,9 @@ (set_attr "mode" "")]) (define_insn_and_split "ssse3_palignrdi" - [(set (match_operand:DI 0 "register_operand" "=y,x,Yv") - (unspec:DI [(match_operand:DI 1 "register_operand" "0,0,Yv") - (match_operand:DI 2 "register_mmxmem_operand" "ym,x,Yv") + [(set (match_operand:DI 0 "register_operand" "=y,x,Yw") + (unspec:DI [(match_operand:DI 1 "register_operand" "0,0,Yw") + (match_operand:DI 2 "register_mmxmem_operand" "ym,x,Yw") (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n,n,n")] UNSPEC_PALIGNR))] "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3" -- 2.7.4