From c3fc7ff876e42ae1fc8872b2c91d8fdd019f2015 Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Tue, 26 May 2009 10:11:50 +0900 Subject: [PATCH] [S5PC100] fix indent Signed-off-by: Minkyu Kang --- include/s5pc1xx.h | 1101 ++++++++++++++++++++++++++--------------------------- 1 file changed, 545 insertions(+), 556 deletions(-) diff --git a/include/s5pc1xx.h b/include/s5pc1xx.h index 24e087f..19ec182 100644 --- a/include/s5pc1xx.h +++ b/include/s5pc1xx.h @@ -1,72 +1,86 @@ /* - * Referenced from linux/arch/arm/plat-s3c/include/plat/ - * & linux/arch/arm/plat-s3c6410/include/plat. + * (C) Copyright 2009 SAMSUNG Electronics + * Heungjun Kim + * Minkyu Kang + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #ifndef __S5PC100_H__ #define __S5PC100_H__ -#define __REG(x) (*(vu_long *)(x)) +#define __REG(x) (*(vu_long *)(x)) -#define S5P_ADDR_BASE (0xe0000000) +#define S5P_ADDR_BASE (0xe0000000) #define S5P_ADDR(x) (S5P_ADDR_BASE + (x)) -#define S5P_PA_ID S5P_ADDR(0x00000000) /* ID Base */ -#define S5P_PA_CLK S5P_ADDR(0x00100000) /* Clock Base */ -#define S5P_PA_PWR S5P_ADDR(0x00108000) /* Power Base */ +#define S5P_PA_ID S5P_ADDR(0x00000000) /* ID Base */ +#define S5P_PA_CLK S5P_ADDR(0x00100000) /* Clock Base */ +#define S5P_PA_PWR S5P_ADDR(0x00108000) /* Power Base */ #define S5P_PA_CLK_OTHERS S5P_ADDR(0x00200000) /* Clock Others Base */ -#define S5P_PA_GPIO S5P_ADDR(0x00300000) /* GPIO Base */ -#define S5P_PA_VIC0 S5P_ADDR(0x04000000) /* Vector Interrupt Controller 0 */ -#define S5P_PA_VIC1 S5P_ADDR(0x04100000) /* Vector Interrupt Controller 1 */ -#define S5P_PA_VIC2 S5P_ADDR(0x04200000) /* Vector Interrupt Controller 2 */ +#define S5P_PA_GPIO S5P_ADDR(0x00300000) /* GPIO Base */ +#define S5P_PA_VIC0 S5P_ADDR(0x04000000) /* Vector Interrupt Controller 0 */ +#define S5P_PA_VIC1 S5P_ADDR(0x04100000) /* Vector Interrupt Controller 1 */ +#define S5P_PA_VIC2 S5P_ADDR(0x04200000) /* Vector Interrupt Controller 2 */ #define S5P_PA_TZIC0 S5P_ADDR(0x05000000) /* TrustZone Interrupt Controller 0 */ #define S5P_PA_TZIC1 S5P_ADDR(0x05100000) /* TrustZone Interrupt Controller 1 */ #define S5P_PA_TZIC2 S5P_ADDR(0x05200000) /* TrustZone Interrupt Controller 2 */ -#define S5P_PA_DMC S5P_ADDR(0x06000000) /* Dram Memory Controller */ +#define S5P_PA_DMC S5P_ADDR(0x06000000) /* Dram Memory Controller */ #define S5P_PA_SROMC S5P_ADDR(0x07000000) /* SROM Controller */ #define S5P_PA_ONENANDC S5P_ADDR(0x07100000) /* OneNand Controller */ #define S5P_PA_PWMTIMER S5P_ADDR(0x0a000000) /* PWM Timer */ #define S5P_PA_WATCHDOG S5P_ADDR(0x0a200000) /* Watchdog Timer */ #define S5P_PA_SYSTEM S5P_ADDR(0x0a100000) /* System Timer */ -#define S5P_PA_RTC S5P_ADDR(0x0a300000) /* RTC */ -#define S5P_PA_UART S5P_ADDR(0x0c000000) /* Uart Base */ - +#define S5P_PA_RTC S5P_ADDR(0x0a300000) /* RTC */ +#define S5P_PA_UART S5P_ADDR(0x0c000000) /* Uart Base */ /* * Chip ID */ -#define S5P_ID(x) (S5P_PA_ID + (x)) +#define S5P_ID(x) (S5P_PA_ID + (x)) #define S5P_PRO_ID S5P_ID(0) -#define S5P_OMR S5P_ID(4) - +#define S5P_OMR S5P_ID(4) /* * Clock control */ -#define S5P_CLKREG(x) (S5P_PA_CLK + (x)) +#define S5P_CLKREG(x) (S5P_PA_CLK + (x)) /* Clock Register */ -#define S5P_APLL_LOCK S5P_CLKREG(0x0) -#define S5P_MPLL_LOCK S5P_CLKREG(0x4) -#define S5P_EPLL_LOCK S5P_CLKREG(0x8) -#define S5P_HPLL_LOCK S5P_CLKREG(0xc) - -#define S5P_APLL_CON S5P_CLKREG(0x100) -#define S5P_MPLL_CON S5P_CLKREG(0x104) -#define S5P_EPLL_CON S5P_CLKREG(0x108) -#define S5P_HPLL_CON S5P_CLKREG(0x10c) - -#define S5P_CLK_SRC0 S5P_CLKREG(0x200) -#define S5P_CLK_SRC1 S5P_CLKREG(0x204) -#define S5P_CLK_SRC2 S5P_CLKREG(0x208) -#define S5P_CLK_SRC3 S5P_CLKREG(0x20c) - -#define S5P_CLK_DIV0 S5P_CLKREG(0x300) -#define S5P_CLK_DIV1 S5P_CLKREG(0x304) -#define S5P_CLK_DIV2 S5P_CLKREG(0x308) -#define S5P_CLK_DIV3 S5P_CLKREG(0x30c) -#define S5P_CLK_DIV4 S5P_CLKREG(0x310) +#define S5P_APLL_LOCK S5P_CLKREG(0x0) +#define S5P_MPLL_LOCK S5P_CLKREG(0x4) +#define S5P_EPLL_LOCK S5P_CLKREG(0x8) +#define S5P_HPLL_LOCK S5P_CLKREG(0xc) + +#define S5P_APLL_CON S5P_CLKREG(0x100) +#define S5P_MPLL_CON S5P_CLKREG(0x104) +#define S5P_EPLL_CON S5P_CLKREG(0x108) +#define S5P_HPLL_CON S5P_CLKREG(0x10c) + +#define S5P_CLK_SRC0 S5P_CLKREG(0x200) +#define S5P_CLK_SRC1 S5P_CLKREG(0x204) +#define S5P_CLK_SRC2 S5P_CLKREG(0x208) +#define S5P_CLK_SRC3 S5P_CLKREG(0x20c) + +#define S5P_CLK_DIV0 S5P_CLKREG(0x300) +#define S5P_CLK_DIV1 S5P_CLKREG(0x304) +#define S5P_CLK_DIV2 S5P_CLKREG(0x308) +#define S5P_CLK_DIV3 S5P_CLKREG(0x30c) +#define S5P_CLK_DIV4 S5P_CLKREG(0x310) #define S5P_CLK_OUT S5P_CLKREG(0x400) @@ -124,14 +138,13 @@ #define S5P_CLK_GATE_SCLK0_REG __REG(S5P_CLK_GATE_SCLK0) #define S5P_CLK_GATE_SCLK1_REG __REG(S5P_CLK_GATE_SCLK1) - /* * Power control */ -#define S5P_PWRREG(x) (S5P_PA_PWR + (x)) +#define S5P_PWRREG(x) (S5P_PA_PWR + (x)) -#define S5P_PWR_CFG S5P_PWRREG(0x0) -#define S5P_EINT_WAKEUP_MASK S5P_PWRREG(0x04) +#define S5P_PWR_CFG S5P_PWRREG(0x0) +#define S5P_EINT_WAKEUP_MASK S5P_PWRREG(0x04) #define S5P_NORMAL_CFG S5P_PWRREG(0x10) #define S5P_STOP_CFG S5P_PWRREG(0x14) #define S5P_SLEEP_CFG S5P_PWRREG(0x18) @@ -139,20 +152,20 @@ #define S5P_OSC_FREQ S5P_PWRREG(0x100) #define S5P_OSC_STABLE S5P_PWRREG(0x104) #define S5P_PWR_STABLE S5P_PWRREG(0x108) -#define S5P_INTERNAL_PWR_STABLE S5P_PWRREG(0x110) +#define S5P_INTERNAL_PWR_STABLE S5P_PWRREG(0x110) #define S5P_CLAMP_STABLE S5P_PWRREG(0x114) -#define S5P_OTHERS S5P_PWRREG(0x200) +#define S5P_OTHERS S5P_PWRREG(0x200) #define S5P_RST_STAT S5P_PWRREG(0x300) #define S5P_WAKEUP_STAT S5P_PWRREG(0x304) #define S5P_BLK_PWR_STAT S5P_PWRREG(0x308) -#define S5P_INFORM0 S5P_PWRREG(0x400) -#define S5P_INFORM1 S5P_PWRREG(0x404) -#define S5P_INFORM2 S5P_PWRREG(0x408) -#define S5P_INFORM3 S5P_PWRREG(0x40c) -#define S5P_INFORM4 S5P_PWRREG(0x410) -#define S5P_INFORM5 S5P_PWRREG(0x414) -#define S5P_INFORM6 S5P_PWRREG(0x418) -#define S5P_INFORM7 S5P_PWRREG(0x41c) +#define S5P_INFORM0 S5P_PWRREG(0x400) +#define S5P_INFORM1 S5P_PWRREG(0x404) +#define S5P_INFORM2 S5P_PWRREG(0x408) +#define S5P_INFORM3 S5P_PWRREG(0x40c) +#define S5P_INFORM4 S5P_PWRREG(0x410) +#define S5P_INFORM5 S5P_PWRREG(0x414) +#define S5P_INFORM6 S5P_PWRREG(0x418) +#define S5P_INFORM7 S5P_PWRREG(0x41c) #define S5P_DCGIDX_MAP0 S5P_PWRREG(0x500) #define S5P_DCGIDX_MAP1 S5P_PWRREG(0x504) #define S5P_DCGIDX_MAP2 S5P_PWRREG(0x508) @@ -183,19 +196,18 @@ #define S5P_IEM_HPMCLK_DIV S5P_PWRREG(0x724) - /* * Clock control - Others */ -#define S5P_OTHERS_REG_BASE(x) (S5P_PA_CLK_OTHERS + (x)) +#define S5P_OTHERS_REG_BASE(x) (S5P_PA_CLK_OTHERS + (x)) #define S5P_OTHERS_BASE S5P_OTHERS_REG_BASE(0x0) -#define S5P_SW_RST S5P_OTHERS_REG_BASE(0x0) -#define S5P_ONENAND_RST S5P_OTHERS_REG_BASE(0x8) +#define S5P_SW_RST S5P_OTHERS_REG_BASE(0x0) +#define S5P_ONENAND_RST S5P_OTHERS_REG_BASE(0x8) #define S5P_GENERAL_CTRL S5P_OTHERS_REG_BASE(0x100) #define S5P_GENERAL_STATUS S5P_OTHERS_REG_BASE(0x104) -#define S5P_MEM_SYS_CFG S5P_OTHERS_REG_BASE(0x200) -#define S5P_CAM_MUX_SEL S5P_OTHERS_REG_BASE(0x300) +#define S5P_MEM_SYS_CFG S5P_OTHERS_REG_BASE(0x200) +#define S5P_CAM_MUX_SEL S5P_OTHERS_REG_BASE(0x300) #define S5P_MIXER_OUT_SEL S5P_OTHERS_REG_BASE(0x304) #define S5P_LPMP3_MODE_SEL S5P_OTHERS_REG_BASE(0x308) #define S5P_MIPI_PHY_CON0 S5P_OTHERS_REG_BASE(0x400) @@ -205,45 +217,45 @@ #define S5P_OTHERS_BASE_REG __REG(S5P_OTHERS_BASE) #define S5P_SW_RST_REG __REG(S5P_SW_RST) #define S5P_ONENAND_RST_REG __REG(S5P_ONENAND_RST) -#define S5P_GENERAL_CTRL_REG __REG(S5P_GENERAL_CTRL) -#define S5P_GENERAL_STATUS_REG __REG(S5P_GENERAL_STATUS) +#define S5P_GENERAL_CTRL_REG __REG(S5P_GENERAL_CTRL) +#define S5P_GENERAL_STATUS_REG __REG(S5P_GENERAL_STATUS) #define S5P_MEM_SYS_CFG_REG __REG(S5P_MEM_SYS_CFG) #define S5P_CAM_MUX_SEL_REG __REG(S5P_CAM_MUX_SEL) -#define S5P_MIXER_OUT_SEL_REG __REG(S5P_MIXER_OUT_SEL) -#define S5P_LPMP3_MODE_SEL_REG __REG(S5P_LPMP3_MODE_SEL) -#define S5P_MIPI_PHY_CON0_REG __REG(S5P_MIPI_PHY_CON0) -#define S5P_MIPI_PHY_CON1_REG __REG(S5P_MIPI_PHY_CON1) -#define S5P_HDMI_PHY_CON0_REG __REG(S5P_HDMI_PHY_CON0) +#define S5P_MIXER_OUT_SEL_REG __REG(S5P_MIXER_OUT_SEL) +#define S5P_LPMP3_MODE_SEL_REG __REG(S5P_LPMP3_MODE_SEL) +#define S5P_MIPI_PHY_CON0_REG __REG(S5P_MIPI_PHY_CON0) +#define S5P_MIPI_PHY_CON1_REG __REG(S5P_MIPI_PHY_CON1) +#define S5P_HDMI_PHY_CON0_REG __REG(S5P_HDMI_PHY_CON0) /* * GPIO */ /* GPIO Bank Base */ -#define S5P_GPIO_BASE(x) (S5P_PA_GPIO + (x)) - -#define S5P_GPIO_A_REG(x) (S5P_GPIO_BASE(0x0) + (x)) -#define S5P_GPIO_B_REG(x) (S5P_GPIO_BASE(0x40) + (x)) -#define S5P_GPIO_C_REG(x) (S5P_GPIO_BASE(0x60) + (x)) -#define S5P_GPIO_D_REG(x) (S5P_GPIO_BASE(0x80) + (x)) -#define S5P_GPIO_E_REG(x) (S5P_GPIO_BASE(0xa0) + (x)) -#define S5P_GPIO_F_REG(x) (S5P_GPIO_BASE(0xe0) + (x)) -#define S5P_GPIO_G_REG(x) (S5P_GPIO_BASE(0x160) + (x)) -#define S5P_GPIO_I_REG(x) (S5P_GPIO_BASE(0x1e0) + (x)) -#define S5P_GPIO_J_REG(x) (S5P_GPIO_BASE(0x200) + (x)) -#define S5P_GPIO_K_REG(x) (S5P_GPIO_BASE(0x2a0) + (x)) -#define S5P_GPIO_L_REG(x) (S5P_GPIO_BASE(0x320) + (x)) - -#define S5P_MP_REG(x) (S5P_GPIO_BASE(0x3c0) + (x)) -#define S5P_ETC_REG(x) (S5P_GPIO_BASE(0x4e0) + (x)) - -#define S5P_GPIO_INT_CON_REG(x) (S5P_GPIO_BASE(0x700) + (x)) +#define S5P_GPIO_BASE(x) (S5P_PA_GPIO + (x)) + +#define S5P_GPIO_A_REG(x) (S5P_GPIO_BASE(0x0) + (x)) +#define S5P_GPIO_B_REG(x) (S5P_GPIO_BASE(0x40) + (x)) +#define S5P_GPIO_C_REG(x) (S5P_GPIO_BASE(0x60) + (x)) +#define S5P_GPIO_D_REG(x) (S5P_GPIO_BASE(0x80) + (x)) +#define S5P_GPIO_E_REG(x) (S5P_GPIO_BASE(0xa0) + (x)) +#define S5P_GPIO_F_REG(x) (S5P_GPIO_BASE(0xe0) + (x)) +#define S5P_GPIO_G_REG(x) (S5P_GPIO_BASE(0x160) + (x)) +#define S5P_GPIO_I_REG(x) (S5P_GPIO_BASE(0x1e0) + (x)) +#define S5P_GPIO_J_REG(x) (S5P_GPIO_BASE(0x200) + (x)) +#define S5P_GPIO_K_REG(x) (S5P_GPIO_BASE(0x2a0) + (x)) +#define S5P_GPIO_L_REG(x) (S5P_GPIO_BASE(0x320) + (x)) + +#define S5P_MP_REG(x) (S5P_GPIO_BASE(0x3c0) + (x)) +#define S5P_ETC_REG(x) (S5P_GPIO_BASE(0x4e0) + (x)) + +#define S5P_GPIO_INT_CON_REG(x) (S5P_GPIO_BASE(0x700) + (x)) #define S5P_GPIO_INT_FLTCON_REG(x) (S5P_GPIO_BASE(0x800) + (x)) #define S5P_GPIO_INT_MASK_REG(x) (S5P_GPIO_BASE(0x900) + (x)) #define S5P_GPIO_INT_PEND_REG(x) (S5P_GPIO_BASE(0xa00) + (x)) #define S5P_GPIO_INT_PRIO_REG(x) (S5P_GPIO_BASE(0xb00) + (x)) -#define S5P_GPIO_H_REG(x) (S5P_GPIO_BASE(0xc00) + (x)) +#define S5P_GPIO_H_REG(x) (S5P_GPIO_BASE(0xc00) + (x)) #define S5P_WAKEUP_INT_CON(x) (S5P_GPIO_BASE(0xe00) + (x)) #define S5P_WAKEUP_FLTINT_CON(x) (S5P_GPIO_BASE(0xe80) + (x)) @@ -256,8 +268,8 @@ #define DAT_OFFSET 0x4 #define PULL_OFFSET 0x8 #define DRV_OFFSET 0xc -#define PDNCON_OFFSET 0x10 -#define PDNPULL_OFFSET 0x14 +#define PDNCON_OFFSET 0x10 +#define PDNPULL_OFFSET 0x14 /* GPIO A Bank Base */ @@ -266,47 +278,47 @@ #define S5P_GPIO_A0_CON S5P_GPIO_A0_BASE(CON_OFFSET) #define S5P_GPIO_A0_DAT S5P_GPIO_A0_BASE(DAT_OFFSET) -#define S5P_GPIO_A0_PULL S5P_GPIO_A0_BASE(PULL_OFFSET) +#define S5P_GPIO_A0_PULL S5P_GPIO_A0_BASE(PULL_OFFSET) #define S5P_GPIO_A0_DRV S5P_GPIO_A0_BASE(DRV_OFFSET) -#define S5P_GPIO_A0_PDNCON S5P_GPIO_A0_BASE(PDNCON_OFFSET) -#define S5P_GPIO_A0_PDNPUL S5P_GPIO_A0_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_A0_PDNCON S5P_GPIO_A0_BASE(PDNCON_OFFSET) +#define S5P_GPIO_A0_PDNPUL S5P_GPIO_A0_BASE(PDNPULL_OFFSET) #define S5P_GPIO_A1_CON S5P_GPIO_A1_BASE(CON_OFFSET) #define S5P_GPIO_A1_DAT S5P_GPIO_A1_BASE(DAT_OFFSET) -#define S5P_GPIO_A1_PULL S5P_GPIO_A1_BASE(PULL_OFFSET) +#define S5P_GPIO_A1_PULL S5P_GPIO_A1_BASE(PULL_OFFSET) #define S5P_GPIO_A1_DRV S5P_GPIO_A1_BASE(DRV_OFFSET) -#define S5P_GPIO_A1_PDNCON S5P_GPIO_A1_BASE(PDNCON_OFFSET) -#define S5P_GPIO_A1_PDNPUL S5P_GPIO_A1_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_A1_PDNCON S5P_GPIO_A1_BASE(PDNCON_OFFSET) +#define S5P_GPIO_A1_PDNPUL S5P_GPIO_A1_BASE(PDNPULL_OFFSET) /* GPIO B Bank Base */ -#define S5P_GPIO_B_BASE(x) (S5P_GPIO_B_REG(0x0) + (x)) +#define S5P_GPIO_B_BASE(x) (S5P_GPIO_B_REG(0x0) + (x)) -#define S5P_GPIO_B_CON S5P_GPIO_B_BASE(CON_OFFSET) -#define S5P_GPIO_B_DAT S5P_GPIO_B_BASE(DAT_OFFSET) +#define S5P_GPIO_B_CON S5P_GPIO_B_BASE(CON_OFFSET) +#define S5P_GPIO_B_DAT S5P_GPIO_B_BASE(DAT_OFFSET) #define S5P_GPIO_B_PULL S5P_GPIO_B_BASE(PULL_OFFSET) -#define S5P_GPIO_B_DRV S5P_GPIO_B_BASE(DRV_OFFSET) -#define S5P_GPIO_B_PDNCON S5P_GPIO_B_BASE(PDNCON_OFFSET) -#define S5P_GPIO_B_PDNPUL S5P_GPIO_B_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_B_DRV S5P_GPIO_B_BASE(DRV_OFFSET) +#define S5P_GPIO_B_PDNCON S5P_GPIO_B_BASE(PDNCON_OFFSET) +#define S5P_GPIO_B_PDNPUL S5P_GPIO_B_BASE(PDNPULL_OFFSET) /* GPIO C Bank Base */ -#define S5P_GPIO_C_BASE(x) (S5P_GPIO_C_REG(0x0) + (x)) +#define S5P_GPIO_C_BASE(x) (S5P_GPIO_C_REG(0x0) + (x)) -#define S5P_GPIO_C_CON S5P_GPIO_C_BASE(CON_OFFSET) -#define S5P_GPIO_C_DAT S5P_GPIO_C_BASE(DAT_OFFSET) +#define S5P_GPIO_C_CON S5P_GPIO_C_BASE(CON_OFFSET) +#define S5P_GPIO_C_DAT S5P_GPIO_C_BASE(DAT_OFFSET) #define S5P_GPIO_C_PULL S5P_GPIO_C_BASE(PULL_OFFSET) -#define S5P_GPIO_C_DRV S5P_GPIO_C_BASE(DRV_OFFSET) -#define S5P_GPIO_C_PDNCON S5P_GPIO_C_BASE(PDNCON_OFFSET) -#define S5P_GPIO_C_PDNPUL S5P_GPIO_C_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_C_DRV S5P_GPIO_C_BASE(DRV_OFFSET) +#define S5P_GPIO_C_PDNCON S5P_GPIO_C_BASE(PDNCON_OFFSET) +#define S5P_GPIO_C_PDNPUL S5P_GPIO_C_BASE(PDNPULL_OFFSET) /* GPIO D Bank Base */ -#define S5P_GPIO_D_BASE(x) (S5P_GPIO_C_REG(0x0) + (x)) +#define S5P_GPIO_D_BASE(x) (S5P_GPIO_C_REG(0x0) + (x)) -#define S5P_GPIO_D_CON S5P_GPIO_C_BASE(CON_OFFSET) -#define S5P_GPIO_D_DAT S5P_GPIO_C_BASE(DAT_OFFSET) +#define S5P_GPIO_D_CON S5P_GPIO_C_BASE(CON_OFFSET) +#define S5P_GPIO_D_DAT S5P_GPIO_C_BASE(DAT_OFFSET) #define S5P_GPIO_D_PULL S5P_GPIO_C_BASE(PULL_OFFSET) -#define S5P_GPIO_D_DRV S5P_GPIO_C_BASE(DRV_OFFSET) -#define S5P_GPIO_D_PDNCON S5P_GPIO_C_BASE(PDNCON_OFFSET) -#define S5P_GPIO_D_PDNPUL S5P_GPIO_C_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_D_DRV S5P_GPIO_C_BASE(DRV_OFFSET) +#define S5P_GPIO_D_PDNCON S5P_GPIO_C_BASE(PDNCON_OFFSET) +#define S5P_GPIO_D_PDNPUL S5P_GPIO_C_BASE(PDNPULL_OFFSET) /* GPIO E Bank Base */ #define S5P_GPIO_E0_BASE(x) (S5P_GPIO_E_REG(0x0) + (x)) @@ -314,17 +326,17 @@ #define S5P_GPIO_E0_CON S5P_GPIO_E0_BASE(CON_OFFSET) #define S5P_GPIO_E0_DAT S5P_GPIO_E0_BASE(DAT_OFFSET) -#define S5P_GPIO_E0_PULL S5P_GPIO_E0_BASE(PULL_OFFSET) +#define S5P_GPIO_E0_PULL S5P_GPIO_E0_BASE(PULL_OFFSET) #define S5P_GPIO_E0_DRV S5P_GPIO_E0_BASE(DRV_OFFSET) -#define S5P_GPIO_E0_PDNCON S5P_GPIO_E0_BASE(PDNCON_OFFSET) -#define S5P_GPIO_E0_PDNPUL S5P_GPIO_E0_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_E0_PDNCON S5P_GPIO_E0_BASE(PDNCON_OFFSET) +#define S5P_GPIO_E0_PDNPUL S5P_GPIO_E0_BASE(PDNPULL_OFFSET) #define S5P_GPIO_E1_CON S5P_GPIO_E1_BASE(CON_OFFSET) #define S5P_GPIO_E1_DAT S5P_GPIO_E1_BASE(DAT_OFFSET) -#define S5P_GPIO_E1_PULL S5P_GPIO_E1_BASE(PULL_OFFSET) +#define S5P_GPIO_E1_PULL S5P_GPIO_E1_BASE(PULL_OFFSET) #define S5P_GPIO_E1_DRV S5P_GPIO_E1_BASE(DRV_OFFSET) -#define S5P_GPIO_E1_PDNCON S5P_GPIO_E1_BASE(PDNCON_OFFSET) -#define S5P_GPIO_E1_PDNPUL S5P_GPIO_E1_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_E1_PDNCON S5P_GPIO_E1_BASE(PDNCON_OFFSET) +#define S5P_GPIO_E1_PDNPUL S5P_GPIO_E1_BASE(PDNPULL_OFFSET) /* GPIO F Bank Base */ #define S5P_GPIO_F0_BASE(x) (S5P_GPIO_F_REG(0x0) + (x)) @@ -334,31 +346,31 @@ #define S5P_GPIO_F0_CON S5P_GPIO_F0_BASE(CON_OFFSET) #define S5P_GPIO_F0_DAT S5P_GPIO_F0_BASE(DAT_OFFSET) -#define S5P_GPIO_F0_PULL S5P_GPIO_F0_BASE(PULL_OFFSET) +#define S5P_GPIO_F0_PULL S5P_GPIO_F0_BASE(PULL_OFFSET) #define S5P_GPIO_F0_DRV S5P_GPIO_F0_BASE(DRV_OFFSET) -#define S5P_GPIO_F0_PDNCON S5P_GPIO_F0_BASE(PDNCON_OFFSET) -#define S5P_GPIO_F0_PDNPUL S5P_GPIO_F0_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_F0_PDNCON S5P_GPIO_F0_BASE(PDNCON_OFFSET) +#define S5P_GPIO_F0_PDNPUL S5P_GPIO_F0_BASE(PDNPULL_OFFSET) #define S5P_GPIO_F1_CON S5P_GPIO_F1_BASE(CON_OFFSET) #define S5P_GPIO_F1_DAT S5P_GPIO_F1_BASE(DAT_OFFSET) -#define S5P_GPIO_F1_PULL S5P_GPIO_F1_BASE(PULL_OFFSET) +#define S5P_GPIO_F1_PULL S5P_GPIO_F1_BASE(PULL_OFFSET) #define S5P_GPIO_F1_DRV S5P_GPIO_F1_BASE(DRV_OFFSET) -#define S5P_GPIO_F1_PDNCON S5P_GPIO_F1_BASE(PDNCON_OFFSET) -#define S5P_GPIO_F1_PDNPUL S5P_GPIO_F1_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_F1_PDNCON S5P_GPIO_F1_BASE(PDNCON_OFFSET) +#define S5P_GPIO_F1_PDNPUL S5P_GPIO_F1_BASE(PDNPULL_OFFSET) #define S5P_GPIO_F2_CON S5P_GPIO_F2_BASE(CON_OFFSET) #define S5P_GPIO_F2_DAT S5P_GPIO_F2_BASE(DAT_OFFSET) -#define S5P_GPIO_F2_PULL S5P_GPIO_F2_BASE(PULL_OFFSET) +#define S5P_GPIO_F2_PULL S5P_GPIO_F2_BASE(PULL_OFFSET) #define S5P_GPIO_F2_DRV S5P_GPIO_F2_BASE(DRV_OFFSET) -#define S5P_GPIO_F2_PDNCON S5P_GPIO_F2_BASE(PDNCON_OFFSET) -#define S5P_GPIO_F2_PDNPUL S5P_GPIO_F2_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_F2_PDNCON S5P_GPIO_F2_BASE(PDNCON_OFFSET) +#define S5P_GPIO_F2_PDNPUL S5P_GPIO_F2_BASE(PDNPULL_OFFSET) #define S5P_GPIO_F3_CON S5P_GPIO_F3_BASE(CON_OFFSET) #define S5P_GPIO_F3_DAT S5P_GPIO_F3_BASE(DAT_OFFSET) -#define S5P_GPIO_F3_PULL S5P_GPIO_F3_BASE(PULL_OFFSET) +#define S5P_GPIO_F3_PULL S5P_GPIO_F3_BASE(PULL_OFFSET) #define S5P_GPIO_F3_DRV S5P_GPIO_F3_BASE(DRV_OFFSET) -#define S5P_GPIO_F3_PDNCON S5P_GPIO_F3_BASE(PDNCON_OFFSET) -#define S5P_GPIO_F3_PDNPUL S5P_GPIO_F3_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_F3_PDNCON S5P_GPIO_F3_BASE(PDNCON_OFFSET) +#define S5P_GPIO_F3_PDNPUL S5P_GPIO_F3_BASE(PDNPULL_OFFSET) /* GPIO G Bank Base */ #define S5P_GPIO_G0_BASE(x) (S5P_GPIO_G_REG(0x0) + (x)) @@ -368,41 +380,41 @@ #define S5P_GPIO_G0_CON S5P_GPIO_G0_BASE(CON_OFFSET) #define S5P_GPIO_G0_DAT S5P_GPIO_G0_BASE(DAT_OFFSET) -#define S5P_GPIO_G0_PULL S5P_GPIO_G0_BASE(PULL_OFFSET) +#define S5P_GPIO_G0_PULL S5P_GPIO_G0_BASE(PULL_OFFSET) #define S5P_GPIO_G0_DRV S5P_GPIO_G0_BASE(DRV_OFFSET) -#define S5P_GPIO_G0_PDNCON S5P_GPIO_G0_BASE(PDNCON_OFFSET) -#define S5P_GPIO_G0_PDNPUL S5P_GPIO_G0_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_G0_PDNCON S5P_GPIO_G0_BASE(PDNCON_OFFSET) +#define S5P_GPIO_G0_PDNPUL S5P_GPIO_G0_BASE(PDNPULL_OFFSET) #define S5P_GPIO_G1_CON S5P_GPIO_G1_BASE(CON_OFFSET) #define S5P_GPIO_G1_DAT S5P_GPIO_G1_BASE(DAT_OFFSET) -#define S5P_GPIO_G1_PULL S5P_GPIO_G1_BASE(PULL_OFFSET) +#define S5P_GPIO_G1_PULL S5P_GPIO_G1_BASE(PULL_OFFSET) #define S5P_GPIO_G1_DRV S5P_GPIO_G1_BASE(DRV_OFFSET) -#define S5P_GPIO_G1_PDNCON S5P_GPIO_G1_BASE(PDNCON_OFFSET) -#define S5P_GPIO_G1_PDNPUL S5P_GPIO_G1_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_G1_PDNCON S5P_GPIO_G1_BASE(PDNCON_OFFSET) +#define S5P_GPIO_G1_PDNPUL S5P_GPIO_G1_BASE(PDNPULL_OFFSET) #define S5P_GPIO_G2_CON S5P_GPIO_G2_BASE(CON_OFFSET) #define S5P_GPIO_G2_DAT S5P_GPIO_G2_BASE(DAT_OFFSET) -#define S5P_GPIO_G2_PULL S5P_GPIO_G2_BASE(PULL_OFFSET) +#define S5P_GPIO_G2_PULL S5P_GPIO_G2_BASE(PULL_OFFSET) #define S5P_GPIO_G2_DRV S5P_GPIO_G2_BASE(DRV_OFFSET) -#define S5P_GPIO_G2_PDNCON S5P_GPIO_G2_BASE(PDNCON_OFFSET) -#define S5P_GPIO_G2_PDNPUL S5P_GPIO_G2_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_G2_PDNCON S5P_GPIO_G2_BASE(PDNCON_OFFSET) +#define S5P_GPIO_G2_PDNPUL S5P_GPIO_G2_BASE(PDNPULL_OFFSET) #define S5P_GPIO_G3_CON S5P_GPIO_G3_BASE(CON_OFFSET) #define S5P_GPIO_G3_DAT S5P_GPIO_G3_BASE(DAT_OFFSET) -#define S5P_GPIO_G3_PULL S5P_GPIO_G3_BASE(PULL_OFFSET) +#define S5P_GPIO_G3_PULL S5P_GPIO_G3_BASE(PULL_OFFSET) #define S5P_GPIO_G3_DRV S5P_GPIO_G3_BASE(DRV_OFFSET) -#define S5P_GPIO_G3_PDNCON S5P_GPIO_G3_BASE(PDNCON_OFFSET) -#define S5P_GPIO_G3_PDNPUL S5P_GPIO_G3_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_G3_PDNCON S5P_GPIO_G3_BASE(PDNCON_OFFSET) +#define S5P_GPIO_G3_PDNPUL S5P_GPIO_G3_BASE(PDNPULL_OFFSET) /* GPIO I Bank Base */ -#define S5P_GPIO_I_BASE(x) (S5P_GPIO_I_REG(0x0) + (x)) +#define S5P_GPIO_I_BASE(x) (S5P_GPIO_I_REG(0x0) + (x)) -#define S5P_GPIO_I_CON S5P_GPIO_I_BASE(CON_OFFSET) -#define S5P_GPIO_I_DAT S5P_GPIO_I_BASE(DAT_OFFSET) +#define S5P_GPIO_I_CON S5P_GPIO_I_BASE(CON_OFFSET) +#define S5P_GPIO_I_DAT S5P_GPIO_I_BASE(DAT_OFFSET) #define S5P_GPIO_I_PULL S5P_GPIO_I_BASE(PULL_OFFSET) -#define S5P_GPIO_I_DRV S5P_GPIO_I_BASE(DRV_OFFSET) -#define S5P_GPIO_I_PDNCON S5P_GPIO_I_BASE(PDNCON_OFFSET) -#define S5P_GPIO_I_PDNPUL S5P_GPIO_I_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_I_DRV S5P_GPIO_I_BASE(DRV_OFFSET) +#define S5P_GPIO_I_PDNCON S5P_GPIO_I_BASE(PDNCON_OFFSET) +#define S5P_GPIO_I_PDNPUL S5P_GPIO_I_BASE(PDNPULL_OFFSET) /* GPIO J Bank Base */ #define S5P_GPIO_J0_BASE(x) (S5P_GPIO_J_REG(0x0) + (x)) @@ -413,38 +425,38 @@ #define S5P_GPIO_J0_CON S5P_GPIO_J0_BASE(CON_OFFSET) #define S5P_GPIO_J0_DAT S5P_GPIO_J0_BASE(DAT_OFFSET) -#define S5P_GPIO_J0_PULL S5P_GPIO_J0_BASE(PULL_OFFSET) +#define S5P_GPIO_J0_PULL S5P_GPIO_J0_BASE(PULL_OFFSET) #define S5P_GPIO_J0_DRV S5P_GPIO_J0_BASE(DRV_OFFSET) -#define S5P_GPIO_J0_PDNCON S5P_GPIO_J0_BASE(PDNCON_OFFSET) -#define S5P_GPIO_J0_PDNPUL S5P_GPIO_J0_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_J0_PDNCON S5P_GPIO_J0_BASE(PDNCON_OFFSET) +#define S5P_GPIO_J0_PDNPUL S5P_GPIO_J0_BASE(PDNPULL_OFFSET) #define S5P_GPIO_J1_CON S5P_GPIO_J1_BASE(CON_OFFSET) #define S5P_GPIO_J1_DAT S5P_GPIO_J1_BASE(DAT_OFFSET) -#define S5P_GPIO_J1_PULL S5P_GPIO_J1_BASE(PULL_OFFSET) +#define S5P_GPIO_J1_PULL S5P_GPIO_J1_BASE(PULL_OFFSET) #define S5P_GPIO_J1_DRV S5P_GPIO_J1_BASE(DRV_OFFSET) -#define S5P_GPIO_J1_PDNCON S5P_GPIO_J1_BASE(PDNCON_OFFSET) -#define S5P_GPIO_J1_PDNPUL S5P_GPIO_J1_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_J1_PDNCON S5P_GPIO_J1_BASE(PDNCON_OFFSET) +#define S5P_GPIO_J1_PDNPUL S5P_GPIO_J1_BASE(PDNPULL_OFFSET) #define S5P_GPIO_J2_CON S5P_GPIO_J2_BASE(CON_OFFSET) #define S5P_GPIO_J2_DAT S5P_GPIO_J2_BASE(DAT_OFFSET) -#define S5P_GPIO_J2_PULL S5P_GPIO_J2_BASE(PULL_OFFSET) +#define S5P_GPIO_J2_PULL S5P_GPIO_J2_BASE(PULL_OFFSET) #define S5P_GPIO_J2_DRV S5P_GPIO_J2_BASE(DRV_OFFSET) -#define S5P_GPIO_J2_PDNCON S5P_GPIO_J2_BASE(PDNCON_OFFSET) -#define S5P_GPIO_J2_PDNPUL S5P_GPIO_J2_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_J2_PDNCON S5P_GPIO_J2_BASE(PDNCON_OFFSET) +#define S5P_GPIO_J2_PDNPUL S5P_GPIO_J2_BASE(PDNPULL_OFFSET) #define S5P_GPIO_J3_CON S5P_GPIO_J3_BASE(CON_OFFSET) #define S5P_GPIO_J3_DAT S5P_GPIO_J3_BASE(DAT_OFFSET) -#define S5P_GPIO_J3_PULL S5P_GPIO_J3_BASE(PULL_OFFSET) +#define S5P_GPIO_J3_PULL S5P_GPIO_J3_BASE(PULL_OFFSET) #define S5P_GPIO_J3_DRV S5P_GPIO_J3_BASE(DRV_OFFSET) -#define S5P_GPIO_J3_PDNCON S5P_GPIO_J3_BASE(PDNCON_OFFSET) -#define S5P_GPIO_J3_PDNPUL S5P_GPIO_J3_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_J3_PDNCON S5P_GPIO_J3_BASE(PDNCON_OFFSET) +#define S5P_GPIO_J3_PDNPUL S5P_GPIO_J3_BASE(PDNPULL_OFFSET) #define S5P_GPIO_J4_CON S5P_GPIO_J4_BASE(CON_OFFSET) #define S5P_GPIO_J4_DAT S5P_GPIO_J4_BASE(DAT_OFFSET) -#define S5P_GPIO_J4_PULL S5P_GPIO_J4_BASE(PULL_OFFSET) +#define S5P_GPIO_J4_PULL S5P_GPIO_J4_BASE(PULL_OFFSET) #define S5P_GPIO_J4_DRV S5P_GPIO_J4_BASE(DRV_OFFSET) -#define S5P_GPIO_J4_PDNCON S5P_GPIO_J4_BASE(PDNCON_OFFSET) -#define S5P_GPIO_J4_PDNPUL S5P_GPIO_J4_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_J4_PDNCON S5P_GPIO_J4_BASE(PDNCON_OFFSET) +#define S5P_GPIO_J4_PDNPUL S5P_GPIO_J4_BASE(PDNPULL_OFFSET) /* GPIO K Bank Base */ #define S5P_GPIO_K0_BASE(x) (S5P_GPIO_K_REG(0x0) + (x)) @@ -454,31 +466,31 @@ #define S5P_GPIO_K0_CON S5P_GPIO_K0_BASE(CON_OFFSET) #define S5P_GPIO_K0_DAT S5P_GPIO_K0_BASE(DAT_OFFSET) -#define S5P_GPIO_K0_PULL S5P_GPIO_K0_BASE(PULL_OFFSET) +#define S5P_GPIO_K0_PULL S5P_GPIO_K0_BASE(PULL_OFFSET) #define S5P_GPIO_K0_DRV S5P_GPIO_K0_BASE(DRV_OFFSET) -#define S5P_GPIO_K0_PDNCON S5P_GPIO_K0_BASE(PDNCON_OFFSET) -#define S5P_GPIO_K0_PDNPUL S5P_GPIO_K0_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_K0_PDNCON S5P_GPIO_K0_BASE(PDNCON_OFFSET) +#define S5P_GPIO_K0_PDNPUL S5P_GPIO_K0_BASE(PDNPULL_OFFSET) #define S5P_GPIO_K1_CON S5P_GPIO_K1_BASE(CON_OFFSET) #define S5P_GPIO_K1_DAT S5P_GPIO_K1_BASE(DAT_OFFSET) -#define S5P_GPIO_K1_PULL S5P_GPIO_K1_BASE(PULL_OFFSET) +#define S5P_GPIO_K1_PULL S5P_GPIO_K1_BASE(PULL_OFFSET) #define S5P_GPIO_K1_DRV S5P_GPIO_K1_BASE(DRV_OFFSET) -#define S5P_GPIO_K1_PDNCON S5P_GPIO_K1_BASE(PDNCON_OFFSET) -#define S5P_GPIO_K1_PDNPUL S5P_GPIO_K1_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_K1_PDNCON S5P_GPIO_K1_BASE(PDNCON_OFFSET) +#define S5P_GPIO_K1_PDNPUL S5P_GPIO_K1_BASE(PDNPULL_OFFSET) #define S5P_GPIO_K2_CON S5P_GPIO_K2_BASE(CON_OFFSET) #define S5P_GPIO_K2_DAT S5P_GPIO_K2_BASE(DAT_OFFSET) -#define S5P_GPIO_K2_PULL S5P_GPIO_K2_BASE(PULL_OFFSET) +#define S5P_GPIO_K2_PULL S5P_GPIO_K2_BASE(PULL_OFFSET) #define S5P_GPIO_K2_DRV S5P_GPIO_K2_BASE(DRV_OFFSET) -#define S5P_GPIO_K2_PDNCON S5P_GPIO_K2_BASE(PDNCON_OFFSET) -#define S5P_GPIO_K2_PDNPUL S5P_GPIO_K2_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_K2_PDNCON S5P_GPIO_K2_BASE(PDNCON_OFFSET) +#define S5P_GPIO_K2_PDNPUL S5P_GPIO_K2_BASE(PDNPULL_OFFSET) #define S5P_GPIO_K3_CON S5P_GPIO_K3_BASE(CON_OFFSET) #define S5P_GPIO_K3_DAT S5P_GPIO_K3_BASE(DAT_OFFSET) -#define S5P_GPIO_K3_PULL S5P_GPIO_K3_BASE(PULL_OFFSET) +#define S5P_GPIO_K3_PULL S5P_GPIO_K3_BASE(PULL_OFFSET) #define S5P_GPIO_K3_DRV S5P_GPIO_K3_BASE(DRV_OFFSET) -#define S5P_GPIO_K3_PDNCON S5P_GPIO_K3_BASE(PDNCON_OFFSET) -#define S5P_GPIO_K3_PDNPUL S5P_GPIO_K3_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_K3_PDNCON S5P_GPIO_K3_BASE(PDNCON_OFFSET) +#define S5P_GPIO_K3_PDNPUL S5P_GPIO_K3_BASE(PDNPULL_OFFSET) /* GPIO L Bank */ #define S5P_GPIO_L0_BASE(x) (S5P_GPIO_L_REG(0x0) + (x)) @@ -489,228 +501,228 @@ #define S5P_GPIO_L0_CON S5P_GPIO_L0_BASE(CON_OFFSET) #define S5P_GPIO_L0_DAT S5P_GPIO_L0_BASE(DAT_OFFSET) -#define S5P_GPIO_L0_PULL S5P_GPIO_L0_BASE(PULL_OFFSET) +#define S5P_GPIO_L0_PULL S5P_GPIO_L0_BASE(PULL_OFFSET) #define S5P_GPIO_L0_DRV S5P_GPIO_L0_BASE(DRV_OFFSET) -#define S5P_GPIO_L0_PDNCON S5P_GPIO_L0_BASE(PDNCON_OFFSET) -#define S5P_GPIO_L0_PDNPUL S5P_GPIO_L0_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_L0_PDNCON S5P_GPIO_L0_BASE(PDNCON_OFFSET) +#define S5P_GPIO_L0_PDNPUL S5P_GPIO_L0_BASE(PDNPULL_OFFSET) #define S5P_GPIO_L1_CON S5P_GPIO_L1_BASE(CON_OFFSET) #define S5P_GPIO_L1_DAT S5P_GPIO_L1_BASE(DAT_OFFSET) -#define S5P_GPIO_L1_PULL S5P_GPIO_L1_BASE(PULL_OFFSET) +#define S5P_GPIO_L1_PULL S5P_GPIO_L1_BASE(PULL_OFFSET) #define S5P_GPIO_L1_DRV S5P_GPIO_L1_BASE(DRV_OFFSET) -#define S5P_GPIO_L1_PDNCON S5P_GPIO_L1_BASE(PDNCON_OFFSET) -#define S5P_GPIO_L1_PDNPUL S5P_GPIO_L1_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_L1_PDNCON S5P_GPIO_L1_BASE(PDNCON_OFFSET) +#define S5P_GPIO_L1_PDNPUL S5P_GPIO_L1_BASE(PDNPULL_OFFSET) #define S5P_GPIO_L2_CON S5P_GPIO_L2_BASE(CON_OFFSET) #define S5P_GPIO_L2_DAT S5P_GPIO_L2_BASE(DAT_OFFSET) -#define S5P_GPIO_L2_PULL S5P_GPIO_L2_BASE(PULL_OFFSET) +#define S5P_GPIO_L2_PULL S5P_GPIO_L2_BASE(PULL_OFFSET) #define S5P_GPIO_L2_DRV S5P_GPIO_L2_BASE(DRV_OFFSET) -#define S5P_GPIO_L2_PDNCON S5P_GPIO_L2_BASE(PDNCON_OFFSET) -#define S5P_GPIO_L2_PDNPUL S5P_GPIO_L2_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_L2_PDNCON S5P_GPIO_L2_BASE(PDNCON_OFFSET) +#define S5P_GPIO_L2_PDNPUL S5P_GPIO_L2_BASE(PDNPULL_OFFSET) #define S5P_GPIO_L3_CON S5P_GPIO_L3_BASE(CON_OFFSET) #define S5P_GPIO_L3_DAT S5P_GPIO_L3_BASE(DAT_OFFSET) -#define S5P_GPIO_L3_PULL S5P_GPIO_L3_BASE(PULL_OFFSET) +#define S5P_GPIO_L3_PULL S5P_GPIO_L3_BASE(PULL_OFFSET) #define S5P_GPIO_L3_DRV S5P_GPIO_L3_BASE(DRV_OFFSET) -#define S5P_GPIO_L3_PDNCON S5P_GPIO_L3_BASE(PDNCON_OFFSET) -#define S5P_GPIO_L3_PDNPUL S5P_GPIO_L3_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_L3_PDNCON S5P_GPIO_L3_BASE(PDNCON_OFFSET) +#define S5P_GPIO_L3_PDNPUL S5P_GPIO_L3_BASE(PDNPULL_OFFSET) #define S5P_GPIO_L4_CON S5P_GPIO_L4_BASE(CON_OFFSET) #define S5P_GPIO_L4_DAT S5P_GPIO_L4_BASE(DAT_OFFSET) -#define S5P_GPIO_L4_PULL S5P_GPIO_L4_BASE(PULL_OFFSET) +#define S5P_GPIO_L4_PULL S5P_GPIO_L4_BASE(PULL_OFFSET) #define S5P_GPIO_L4_DRV S5P_GPIO_L4_BASE(DRV_OFFSET) -#define S5P_GPIO_L4_PDNCON S5P_GPIO_L4_BASE(PDNCON_OFFSET) -#define S5P_GPIO_L4_PDNPUL S5P_GPIO_L4_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_L4_PDNCON S5P_GPIO_L4_BASE(PDNCON_OFFSET) +#define S5P_GPIO_L4_PDNPUL S5P_GPIO_L4_BASE(PDNPULL_OFFSET) /* GPIO MP Bank */ -#define S5P_MP_0_OFFSET 0x0 -#define S5P_MP_1_OFFSET 0x20 -#define S5P_MP_2_OFFSET 0x40 -#define S5P_MP_3_OFFSET 0x60 -#define S5P_MP_4_OFFSET 0x80 -#define S5P_MP_5_OFFSET 0xa0 -#define S5P_MP_6_OFFSET 0xc0 -#define S5P_MP_7_OFFSET 0xe0 - -#define S5P_MP_0_BASE(x) (S5P_MP_REG(S5P_MP_0_OFFSET) + (x)) -#define S5P_MP_1_BASE(x) (S5P_MP_REG(S5P_MP_1_OFFSET) + (x)) -#define S5P_MP_2_BASE(x) (S5P_MP_REG(S5P_MP_2_OFFSET) + (x)) -#define S5P_MP_3_BASE(x) (S5P_MP_REG(S5P_MP_3_OFFSET) + (x)) -#define S5P_MP_4_BASE(x) (S5P_MP_REG(S5P_MP_4_OFFSET) + (x)) -#define S5P_MP_5_BASE(x) (S5P_MP_REG(S5P_MP_5_OFFSET) + (x)) -#define S5P_MP_6_BASE(x) (S5P_MP_REG(S5P_MP_6_OFFSET) + (x)) -#define S5P_MP_7_BASE(x) (S5P_MP_REG(S5P_MP_7_OFFSET) + (x)) - -#define S5P_MP_0PULL S5P_MP_0_BASE(PULL_OFFSET) -#define S5P_MP_0DRV S5P_MP_0_BASE(DRV_OFFSET) +#define S5P_MP_0_OFFSET 0x0 +#define S5P_MP_1_OFFSET 0x20 +#define S5P_MP_2_OFFSET 0x40 +#define S5P_MP_3_OFFSET 0x60 +#define S5P_MP_4_OFFSET 0x80 +#define S5P_MP_5_OFFSET 0xa0 +#define S5P_MP_6_OFFSET 0xc0 +#define S5P_MP_7_OFFSET 0xe0 + +#define S5P_MP_0_BASE(x) (S5P_MP_REG(S5P_MP_0_OFFSET) + (x)) +#define S5P_MP_1_BASE(x) (S5P_MP_REG(S5P_MP_1_OFFSET) + (x)) +#define S5P_MP_2_BASE(x) (S5P_MP_REG(S5P_MP_2_OFFSET) + (x)) +#define S5P_MP_3_BASE(x) (S5P_MP_REG(S5P_MP_3_OFFSET) + (x)) +#define S5P_MP_4_BASE(x) (S5P_MP_REG(S5P_MP_4_OFFSET) + (x)) +#define S5P_MP_5_BASE(x) (S5P_MP_REG(S5P_MP_5_OFFSET) + (x)) +#define S5P_MP_6_BASE(x) (S5P_MP_REG(S5P_MP_6_OFFSET) + (x)) +#define S5P_MP_7_BASE(x) (S5P_MP_REG(S5P_MP_7_OFFSET) + (x)) + +#define S5P_MP_0PULL S5P_MP_0_BASE(PULL_OFFSET) +#define S5P_MP_0DRV S5P_MP_0_BASE(DRV_OFFSET) #define S5P_MP_0PDNPULL S5P_MP_0_BASE(PDNPULL_OFFSET) -#define S5P_MP_1PULL S5P_MP_1_BASE(PULL_OFFSET) -#define S5P_MP_1DRV S5P_MP_1_BASE(DRV_OFFSET) +#define S5P_MP_1PULL S5P_MP_1_BASE(PULL_OFFSET) +#define S5P_MP_1DRV S5P_MP_1_BASE(DRV_OFFSET) #define S5P_MP_1PDNPULL S5P_MP_1_BASE(PDNPULL_OFFSET) -#define S5P_MP_2PULL S5P_MP_2_BASE(PULL_OFFSET) -#define S5P_MP_2DRV S5P_MP_2_BASE(DRV_OFFSET) +#define S5P_MP_2PULL S5P_MP_2_BASE(PULL_OFFSET) +#define S5P_MP_2DRV S5P_MP_2_BASE(DRV_OFFSET) #define S5P_MP_2PDNPULL S5P_MP_2_BASE(PDNPULL_OFFSET) -#define S5P_MP_3DRV S5P_MP_3_BASE(DRV_OFFSET) -#define S5P_MP_4DRV S5P_MP_4_BASE(DRV_OFFSET) -#define S5P_MP_5DRV S5P_MP_5_BASE(DRV_OFFSET) -#define S5P_MP_6DRV S5P_MP_6_BASE(DRV_OFFSET) -#define S5P_MP_7DRV S5P_MP_7_BASE(DRV_OFFSET) -#define S5P_MP_8DRV S5P_MP_8_BASE(DRV_OFFSET) +#define S5P_MP_3DRV S5P_MP_3_BASE(DRV_OFFSET) +#define S5P_MP_4DRV S5P_MP_4_BASE(DRV_OFFSET) +#define S5P_MP_5DRV S5P_MP_5_BASE(DRV_OFFSET) +#define S5P_MP_6DRV S5P_MP_6_BASE(DRV_OFFSET) +#define S5P_MP_7DRV S5P_MP_7_BASE(DRV_OFFSET) +#define S5P_MP_8DRV S5P_MP_8_BASE(DRV_OFFSET) /* GPIO ETC Bank */ -#define S5P_ETC0_BASE(x) (S5P_ETC_REG(0x0) + (x)) -#define S5P_ETC1_BASE(x) (S5P_ETC_REG(0x20) + (x)) -#define S5P_ETC2_BASE(x) (S5P_ETC_REG(0x40) + (x)) -#define S5P_ETC3_BASE(x) (S5P_ETC_REG(0x60) + (x)) -#define S5P_ETC4_BASE(x) (S5P_ETC_REG(0x80) + (x)) - -#define S5P_ETC0PULL S5P_ETC0_BASE(PULL_OFFSET) -#define S5P_ETC0DRV S5P_ETC0_BASE(DRV_OFFSET) -#define S5P_ETC1PULL S5P_ETC1_BASE(PULL_OFFSET) -#define S5P_ETC1DRV S5P_ETC1_BASE(DRV_OFFSET) -#define S5P_ETC2PULL S5P_ETC2_BASE(PULL_OFFSET) -#define S5P_ETC2DRV S5P_ETC2_BASE(DRV_OFFSET) -#define S5P_ETC3PULL S5P_ETC3_BASE(PULL_OFFSET) -#define S5P_ETC3DRV S5P_ETC3_BASE(DRV_OFFSET) -#define S5P_ETC4DRV S5P_ETC4_BASE(DRV_OFFSET) +#define S5P_ETC0_BASE(x) (S5P_ETC_REG(0x0) + (x)) +#define S5P_ETC1_BASE(x) (S5P_ETC_REG(0x20) + (x)) +#define S5P_ETC2_BASE(x) (S5P_ETC_REG(0x40) + (x)) +#define S5P_ETC3_BASE(x) (S5P_ETC_REG(0x60) + (x)) +#define S5P_ETC4_BASE(x) (S5P_ETC_REG(0x80) + (x)) + +#define S5P_ETC0PULL S5P_ETC0_BASE(PULL_OFFSET) +#define S5P_ETC0DRV S5P_ETC0_BASE(DRV_OFFSET) +#define S5P_ETC1PULL S5P_ETC1_BASE(PULL_OFFSET) +#define S5P_ETC1DRV S5P_ETC1_BASE(DRV_OFFSET) +#define S5P_ETC2PULL S5P_ETC2_BASE(PULL_OFFSET) +#define S5P_ETC2DRV S5P_ETC2_BASE(DRV_OFFSET) +#define S5P_ETC3PULL S5P_ETC3_BASE(PULL_OFFSET) +#define S5P_ETC3DRV S5P_ETC3_BASE(DRV_OFFSET) +#define S5P_ETC4DRV S5P_ETC4_BASE(DRV_OFFSET) /* GPIO External Interrupt */ -#define S5P_GPIO_INT0_CON S5P_GPIO_INT_CON_REG(0x0) -#define S5P_GPIO_INT1_CON S5P_GPIO_INT_CON_REG(0x4) -#define S5P_GPIO_INT2_CON S5P_GPIO_INT_CON_REG(0x8) -#define S5P_GPIO_INT3_CON S5P_GPIO_INT_CON_REG(0xc) -#define S5P_GPIO_INT4_CON S5P_GPIO_INT_CON_REG(0x10) -#define S5P_GPIO_INT5_CON S5P_GPIO_INT_CON_REG(0x14) -#define S5P_GPIO_INT6_CON S5P_GPIO_INT_CON_REG(0x18) -#define S5P_GPIO_INT7_CON S5P_GPIO_INT_CON_REG(0x1c) -#define S5P_GPIO_INT8_CON S5P_GPIO_INT_CON_REG(0x20) -#define S5P_GPIO_INT9_CON S5P_GPIO_INT_CON_REG(0x24) -#define S5P_GPIO_INT10_CON S5P_GPIO_INT_CON_REG(0x28) -#define S5P_GPIO_INT11_CON S5P_GPIO_INT_CON_REG(0x2c) -#define S5P_GPIO_INT12_CON S5P_GPIO_INT_CON_REG(0x30) -#define S5P_GPIO_INT13_CON S5P_GPIO_INT_CON_REG(0x34) -#define S5P_GPIO_INT14_CON S5P_GPIO_INT_CON_REG(0x38) -#define S5P_GPIO_INT15_CON S5P_GPIO_INT_CON_REG(0x3c) -#define S5P_GPIO_INT16_CON S5P_GPIO_INT_CON_REG(0x40) -#define S5P_GPIO_INT17_CON S5P_GPIO_INT_CON_REG(0x44) -#define S5P_GPIO_INT18_CON S5P_GPIO_INT_CON_REG(0x48) -#define S5P_GPIO_INT19_CON S5P_GPIO_INT_CON_REG(0x4c) -#define S5P_GPIO_INT20_CON S5P_GPIO_INT_CON_REG(0x50) - -#define S5P_GPIO_INT0_FLTCON0 S5P_GPIO_INT_CON_REG(0x0) -#define S5P_GPIO_INT0_FLTCON1 S5P_GPIO_INT_CON_REG(0x4) -#define S5P_GPIO_INT1_FLTCON0 S5P_GPIO_INT_CON_REG(0x8) -#define S5P_GPIO_INT1_FLTCON1 S5P_GPIO_INT_CON_REG(0xc) -#define S5P_GPIO_INT2_FLTCON0 S5P_GPIO_INT_CON_REG(0x10) -#define S5P_GPIO_INT2_FLTCON1 S5P_GPIO_INT_CON_REG(0x14) -#define S5P_GPIO_INT3_FLTCON0 S5P_GPIO_INT_CON_REG(0x18) -#define S5P_GPIO_INT3_FLTCON1 S5P_GPIO_INT_CON_REG(0x1c) -#define S5P_GPIO_INT4_FLTCON0 S5P_GPIO_INT_CON_REG(0x20) -#define S5P_GPIO_INT4_FLTCON1 S5P_GPIO_INT_CON_REG(0x24) -#define S5P_GPIO_INT5_FLTCON0 S5P_GPIO_INT_CON_REG(0x28) -#define S5P_GPIO_INT5_FLTCON1 S5P_GPIO_INT_CON_REG(0x2c) -#define S5P_GPIO_INT6_FLTCON0 S5P_GPIO_INT_CON_REG(0x30) -#define S5P_GPIO_INT6_FLTCON1 S5P_GPIO_INT_CON_REG(0x34) -#define S5P_GPIO_INT7_FLTCON0 S5P_GPIO_INT_CON_REG(0x38) -#define S5P_GPIO_INT7_FLTCON1 S5P_GPIO_INT_CON_REG(0x3c) -#define S5P_GPIO_INT8_FLTCON0 S5P_GPIO_INT_CON_REG(0x40) -#define S5P_GPIO_INT8_FLTCON1 S5P_GPIO_INT_CON_REG(0x44) -#define S5P_GPIO_INT9_FLTCON0 S5P_GPIO_INT_CON_REG(0x48) -#define S5P_GPIO_INT9_FLTCON1 S5P_GPIO_INT_CON_REG(0x4c) -#define S5P_GPIO_INT10_FLTCON0 S5P_GPIO_INT_CON_REG(0x50) -#define S5P_GPIO_INT11_FLTCON0 S5P_GPIO_INT_CON_REG(0x58) -#define S5P_GPIO_INT11_FLTCON1 S5P_GPIO_INT_CON_REG(0x5c) -#define S5P_GPIO_INT12_FLTCON0 S5P_GPIO_INT_CON_REG(0x60) -#define S5P_GPIO_INT13_FLTCON0 S5P_GPIO_INT_CON_REG(0x68) -#define S5P_GPIO_INT13_FLTCON1 S5P_GPIO_INT_CON_REG(0x6c) -#define S5P_GPIO_INT14_FLTCON0 S5P_GPIO_INT_CON_REG(0x70) -#define S5P_GPIO_INT14_FLTCON1 S5P_GPIO_INT_CON_REG(0x74) -#define S5P_GPIO_INT15_FLTCON0 S5P_GPIO_INT_CON_REG(0x78) -#define S5P_GPIO_INT15_FLTCON1 S5P_GPIO_INT_CON_REG(0x7c) -#define S5P_GPIO_INT16_FLTCON0 S5P_GPIO_INT_CON_REG(0x80) -#define S5P_GPIO_INT16_FLTCON1 S5P_GPIO_INT_CON_REG(0x84) -#define S5P_GPIO_INT17_FLTCON0 S5P_GPIO_INT_CON_REG(0x88) -#define S5P_GPIO_INT17_FLTCON1 S5P_GPIO_INT_CON_REG(0x8c) -#define S5P_GPIO_INT18_FLTCON0 S5P_GPIO_INT_CON_REG(0x90) -#define S5P_GPIO_INT18_FLTCON1 S5P_GPIO_INT_CON_REG(0x94) -#define S5P_GPIO_INT19_FLTCON0 S5P_GPIO_INT_CON_REG(0x98) -#define S5P_GPIO_INT19_FLTCON1 S5P_GPIO_INT_CON_REG(0x9c) -#define S5P_GPIO_INT20_FLTCON0 S5P_GPIO_INT_CON_REG(0xa0) - -#define S5P_GPIO_INT0_MASK S5P_GPIO_INT_MASK_REG(0x00) -#define S5P_GPIO_INT1_MASK S5P_GPIO_INT_MASK_REG(0x04) -#define S5P_GPIO_INT2_MASK S5P_GPIO_INT_MASK_REG(0x08) -#define S5P_GPIO_INT3_MASK S5P_GPIO_INT_MASK_REG(0x0c) -#define S5P_GPIO_INT4_MASK S5P_GPIO_INT_MASK_REG(0x10) -#define S5P_GPIO_INT5_MASK S5P_GPIO_INT_MASK_REG(0x14) -#define S5P_GPIO_INT6_MASK S5P_GPIO_INT_MASK_REG(0x18) -#define S5P_GPIO_INT7_MASK S5P_GPIO_INT_MASK_REG(0x1c) -#define S5P_GPIO_INT8_MASK S5P_GPIO_INT_MASK_REG(0x20) -#define S5P_GPIO_INT9_MASK S5P_GPIO_INT_MASK_REG(0x24) -#define S5P_GPIO_INT10_MASK S5P_GPIO_INT_MASK_REG(0x28) -#define S5P_GPIO_INT11_MASK S5P_GPIO_INT_MASK_REG(0x2c) -#define S5P_GPIO_INT12_MASK S5P_GPIO_INT_MASK_REG(0x30) -#define S5P_GPIO_INT13_MASK S5P_GPIO_INT_MASK_REG(0x34) -#define S5P_GPIO_INT14_MASK S5P_GPIO_INT_MASK_REG(0x38) -#define S5P_GPIO_INT15_MASK S5P_GPIO_INT_MASK_REG(0x3c) -#define S5P_GPIO_INT16_MASK S5P_GPIO_INT_MASK_REG(0x40) -#define S5P_GPIO_INT17_MASK S5P_GPIO_INT_MASK_REG(0x44) -#define S5P_GPIO_INT18_MASK S5P_GPIO_INT_MASK_REG(0x48) -#define S5P_GPIO_INT19_MASK S5P_GPIO_INT_MASK_REG(0x4c) -#define S5P_GPIO_INT20_MASK S5P_GPIO_INT_MASK_REG(0x50) - -#define S5P_GPIO_INT0_PEND S5P_GPIO_INT_PEND_REG(0x00) -#define S5P_GPIO_INT1_PEND S5P_GPIO_INT_PEND_REG(0x04) -#define S5P_GPIO_INT2_PEND S5P_GPIO_INT_PEND_REG(0x08) -#define S5P_GPIO_INT3_PEND S5P_GPIO_INT_PEND_REG(0x0c) -#define S5P_GPIO_INT4_PEND S5P_GPIO_INT_PEND_REG(0x10) -#define S5P_GPIO_INT5_PEND S5P_GPIO_INT_PEND_REG(0x14) -#define S5P_GPIO_INT6_PEND S5P_GPIO_INT_PEND_REG(0x18) -#define S5P_GPIO_INT7_PEND S5P_GPIO_INT_PEND_REG(0x1c) -#define S5P_GPIO_INT8_PEND S5P_GPIO_INT_PEND_REG(0x20) -#define S5P_GPIO_INT9_PEND S5P_GPIO_INT_PEND_REG(0x24) -#define S5P_GPIO_INT10_PEND S5P_GPIO_INT_PEND_REG(0x28) -#define S5P_GPIO_INT11_PEND S5P_GPIO_INT_PEND_REG(0x2c) -#define S5P_GPIO_INT12_PEND S5P_GPIO_INT_PEND_REG(0x30) -#define S5P_GPIO_INT13_PEND S5P_GPIO_INT_PEND_REG(0x34) -#define S5P_GPIO_INT14_PEND S5P_GPIO_INT_PEND_REG(0x38) -#define S5P_GPIO_INT15_PEND S5P_GPIO_INT_PEND_REG(0x3c) -#define S5P_GPIO_INT16_PEND S5P_GPIO_INT_PEND_REG(0x40) -#define S5P_GPIO_INT17_PEND S5P_GPIO_INT_PEND_REG(0x44) -#define S5P_GPIO_INT18_PEND S5P_GPIO_INT_PEND_REG(0x48) -#define S5P_GPIO_INT19_PEND S5P_GPIO_INT_PEND_REG(0x4c) -#define S5P_GPIO_INT20_PEND S5P_GPIO_INT_PEND_REG(0x50) - -#define S5P_GPIO_INT_GRPPRI S5P_GPIO_INT_PRIO_REG(0x00) -#define S5P_GPIO_INT_PRIORITY S5P_GPIO_INT_PRIO_REG(0x04) -#define S5P_GPIO_INT_SERVICE S5P_GPIO_INT_PRIO_REG(0x08) -#define S5P_GPIO_INT_SERVICE_PEND S5P_GPIO_INT_PRIO_REG(0x0c) -#define S5P_GPIO_INT_GRPFIXPRI S5P_GPIO_INT_PRIO_REG(0x10) - -#define S5P_GPIO_INT0_FIXPRI S5P_GPIO_INT_PRIO_REG(0x14) -#define S5P_GPIO_INT1_FIXPRI S5P_GPIO_INT_PRIO_REG(0x18) -#define S5P_GPIO_INT2_FIXPRI S5P_GPIO_INT_PRIO_REG(0x1c) -#define S5P_GPIO_INT3_FIXPRI S5P_GPIO_INT_PRIO_REG(0x20) -#define S5P_GPIO_INT4_FIXPRI S5P_GPIO_INT_PRIO_REG(0x24) -#define S5P_GPIO_INT5_FIXPRI S5P_GPIO_INT_PRIO_REG(0x28) -#define S5P_GPIO_INT6_FIXPRI S5P_GPIO_INT_PRIO_REG(0x2c) -#define S5P_GPIO_INT7_FIXPRI S5P_GPIO_INT_PRIO_REG(0x30) -#define S5P_GPIO_INT8_FIXPRI S5P_GPIO_INT_PRIO_REG(0x34) -#define S5P_GPIO_INT9_FIXPRI S5P_GPIO_INT_PRIO_REG(0x38) -#define S5P_GPIO_INT10_FIXPRI S5P_GPIO_INT_PRIO_REG(0x3c) -#define S5P_GPIO_INT11_FIXPRI S5P_GPIO_INT_PRIO_REG(0x40) -#define S5P_GPIO_INT12_FIXPRI S5P_GPIO_INT_PRIO_REG(0x44) -#define S5P_GPIO_INT13_FIXPRI S5P_GPIO_INT_PRIO_REG(0x48) -#define S5P_GPIO_INT14_FIXPRI S5P_GPIO_INT_PRIO_REG(0x4c) -#define S5P_GPIO_INT15_FIXPRI S5P_GPIO_INT_PRIO_REG(0x50) -#define S5P_GPIO_INT16_FIXPRI S5P_GPIO_INT_PRIO_REG(0x54) -#define S5P_GPIO_INT17_FIXPRI S5P_GPIO_INT_PRIO_REG(0x58) -#define S5P_GPIO_INT18_FIXPRI S5P_GPIO_INT_PRIO_REG(0x5c) -#define S5P_GPIO_INT19_FIXPRI S5P_GPIO_INT_PRIO_REG(0x60) -#define S5P_GPIO_INT20_FIXPRI S5P_GPIO_INT_PRIO_REG(0x64) +#define S5P_GPIO_INT0_CON S5P_GPIO_INT_CON_REG(0x0) +#define S5P_GPIO_INT1_CON S5P_GPIO_INT_CON_REG(0x4) +#define S5P_GPIO_INT2_CON S5P_GPIO_INT_CON_REG(0x8) +#define S5P_GPIO_INT3_CON S5P_GPIO_INT_CON_REG(0xc) +#define S5P_GPIO_INT4_CON S5P_GPIO_INT_CON_REG(0x10) +#define S5P_GPIO_INT5_CON S5P_GPIO_INT_CON_REG(0x14) +#define S5P_GPIO_INT6_CON S5P_GPIO_INT_CON_REG(0x18) +#define S5P_GPIO_INT7_CON S5P_GPIO_INT_CON_REG(0x1c) +#define S5P_GPIO_INT8_CON S5P_GPIO_INT_CON_REG(0x20) +#define S5P_GPIO_INT9_CON S5P_GPIO_INT_CON_REG(0x24) +#define S5P_GPIO_INT10_CON S5P_GPIO_INT_CON_REG(0x28) +#define S5P_GPIO_INT11_CON S5P_GPIO_INT_CON_REG(0x2c) +#define S5P_GPIO_INT12_CON S5P_GPIO_INT_CON_REG(0x30) +#define S5P_GPIO_INT13_CON S5P_GPIO_INT_CON_REG(0x34) +#define S5P_GPIO_INT14_CON S5P_GPIO_INT_CON_REG(0x38) +#define S5P_GPIO_INT15_CON S5P_GPIO_INT_CON_REG(0x3c) +#define S5P_GPIO_INT16_CON S5P_GPIO_INT_CON_REG(0x40) +#define S5P_GPIO_INT17_CON S5P_GPIO_INT_CON_REG(0x44) +#define S5P_GPIO_INT18_CON S5P_GPIO_INT_CON_REG(0x48) +#define S5P_GPIO_INT19_CON S5P_GPIO_INT_CON_REG(0x4c) +#define S5P_GPIO_INT20_CON S5P_GPIO_INT_CON_REG(0x50) + +#define S5P_GPIO_INT0_FLTCON0 S5P_GPIO_INT_CON_REG(0x0) +#define S5P_GPIO_INT0_FLTCON1 S5P_GPIO_INT_CON_REG(0x4) +#define S5P_GPIO_INT1_FLTCON0 S5P_GPIO_INT_CON_REG(0x8) +#define S5P_GPIO_INT1_FLTCON1 S5P_GPIO_INT_CON_REG(0xc) +#define S5P_GPIO_INT2_FLTCON0 S5P_GPIO_INT_CON_REG(0x10) +#define S5P_GPIO_INT2_FLTCON1 S5P_GPIO_INT_CON_REG(0x14) +#define S5P_GPIO_INT3_FLTCON0 S5P_GPIO_INT_CON_REG(0x18) +#define S5P_GPIO_INT3_FLTCON1 S5P_GPIO_INT_CON_REG(0x1c) +#define S5P_GPIO_INT4_FLTCON0 S5P_GPIO_INT_CON_REG(0x20) +#define S5P_GPIO_INT4_FLTCON1 S5P_GPIO_INT_CON_REG(0x24) +#define S5P_GPIO_INT5_FLTCON0 S5P_GPIO_INT_CON_REG(0x28) +#define S5P_GPIO_INT5_FLTCON1 S5P_GPIO_INT_CON_REG(0x2c) +#define S5P_GPIO_INT6_FLTCON0 S5P_GPIO_INT_CON_REG(0x30) +#define S5P_GPIO_INT6_FLTCON1 S5P_GPIO_INT_CON_REG(0x34) +#define S5P_GPIO_INT7_FLTCON0 S5P_GPIO_INT_CON_REG(0x38) +#define S5P_GPIO_INT7_FLTCON1 S5P_GPIO_INT_CON_REG(0x3c) +#define S5P_GPIO_INT8_FLTCON0 S5P_GPIO_INT_CON_REG(0x40) +#define S5P_GPIO_INT8_FLTCON1 S5P_GPIO_INT_CON_REG(0x44) +#define S5P_GPIO_INT9_FLTCON0 S5P_GPIO_INT_CON_REG(0x48) +#define S5P_GPIO_INT9_FLTCON1 S5P_GPIO_INT_CON_REG(0x4c) +#define S5P_GPIO_INT10_FLTCON0 S5P_GPIO_INT_CON_REG(0x50) +#define S5P_GPIO_INT11_FLTCON0 S5P_GPIO_INT_CON_REG(0x58) +#define S5P_GPIO_INT11_FLTCON1 S5P_GPIO_INT_CON_REG(0x5c) +#define S5P_GPIO_INT12_FLTCON0 S5P_GPIO_INT_CON_REG(0x60) +#define S5P_GPIO_INT13_FLTCON0 S5P_GPIO_INT_CON_REG(0x68) +#define S5P_GPIO_INT13_FLTCON1 S5P_GPIO_INT_CON_REG(0x6c) +#define S5P_GPIO_INT14_FLTCON0 S5P_GPIO_INT_CON_REG(0x70) +#define S5P_GPIO_INT14_FLTCON1 S5P_GPIO_INT_CON_REG(0x74) +#define S5P_GPIO_INT15_FLTCON0 S5P_GPIO_INT_CON_REG(0x78) +#define S5P_GPIO_INT15_FLTCON1 S5P_GPIO_INT_CON_REG(0x7c) +#define S5P_GPIO_INT16_FLTCON0 S5P_GPIO_INT_CON_REG(0x80) +#define S5P_GPIO_INT16_FLTCON1 S5P_GPIO_INT_CON_REG(0x84) +#define S5P_GPIO_INT17_FLTCON0 S5P_GPIO_INT_CON_REG(0x88) +#define S5P_GPIO_INT17_FLTCON1 S5P_GPIO_INT_CON_REG(0x8c) +#define S5P_GPIO_INT18_FLTCON0 S5P_GPIO_INT_CON_REG(0x90) +#define S5P_GPIO_INT18_FLTCON1 S5P_GPIO_INT_CON_REG(0x94) +#define S5P_GPIO_INT19_FLTCON0 S5P_GPIO_INT_CON_REG(0x98) +#define S5P_GPIO_INT19_FLTCON1 S5P_GPIO_INT_CON_REG(0x9c) +#define S5P_GPIO_INT20_FLTCON0 S5P_GPIO_INT_CON_REG(0xa0) + +#define S5P_GPIO_INT0_MASK S5P_GPIO_INT_MASK_REG(0x00) +#define S5P_GPIO_INT1_MASK S5P_GPIO_INT_MASK_REG(0x04) +#define S5P_GPIO_INT2_MASK S5P_GPIO_INT_MASK_REG(0x08) +#define S5P_GPIO_INT3_MASK S5P_GPIO_INT_MASK_REG(0x0c) +#define S5P_GPIO_INT4_MASK S5P_GPIO_INT_MASK_REG(0x10) +#define S5P_GPIO_INT5_MASK S5P_GPIO_INT_MASK_REG(0x14) +#define S5P_GPIO_INT6_MASK S5P_GPIO_INT_MASK_REG(0x18) +#define S5P_GPIO_INT7_MASK S5P_GPIO_INT_MASK_REG(0x1c) +#define S5P_GPIO_INT8_MASK S5P_GPIO_INT_MASK_REG(0x20) +#define S5P_GPIO_INT9_MASK S5P_GPIO_INT_MASK_REG(0x24) +#define S5P_GPIO_INT10_MASK S5P_GPIO_INT_MASK_REG(0x28) +#define S5P_GPIO_INT11_MASK S5P_GPIO_INT_MASK_REG(0x2c) +#define S5P_GPIO_INT12_MASK S5P_GPIO_INT_MASK_REG(0x30) +#define S5P_GPIO_INT13_MASK S5P_GPIO_INT_MASK_REG(0x34) +#define S5P_GPIO_INT14_MASK S5P_GPIO_INT_MASK_REG(0x38) +#define S5P_GPIO_INT15_MASK S5P_GPIO_INT_MASK_REG(0x3c) +#define S5P_GPIO_INT16_MASK S5P_GPIO_INT_MASK_REG(0x40) +#define S5P_GPIO_INT17_MASK S5P_GPIO_INT_MASK_REG(0x44) +#define S5P_GPIO_INT18_MASK S5P_GPIO_INT_MASK_REG(0x48) +#define S5P_GPIO_INT19_MASK S5P_GPIO_INT_MASK_REG(0x4c) +#define S5P_GPIO_INT20_MASK S5P_GPIO_INT_MASK_REG(0x50) + +#define S5P_GPIO_INT0_PEND S5P_GPIO_INT_PEND_REG(0x00) +#define S5P_GPIO_INT1_PEND S5P_GPIO_INT_PEND_REG(0x04) +#define S5P_GPIO_INT2_PEND S5P_GPIO_INT_PEND_REG(0x08) +#define S5P_GPIO_INT3_PEND S5P_GPIO_INT_PEND_REG(0x0c) +#define S5P_GPIO_INT4_PEND S5P_GPIO_INT_PEND_REG(0x10) +#define S5P_GPIO_INT5_PEND S5P_GPIO_INT_PEND_REG(0x14) +#define S5P_GPIO_INT6_PEND S5P_GPIO_INT_PEND_REG(0x18) +#define S5P_GPIO_INT7_PEND S5P_GPIO_INT_PEND_REG(0x1c) +#define S5P_GPIO_INT8_PEND S5P_GPIO_INT_PEND_REG(0x20) +#define S5P_GPIO_INT9_PEND S5P_GPIO_INT_PEND_REG(0x24) +#define S5P_GPIO_INT10_PEND S5P_GPIO_INT_PEND_REG(0x28) +#define S5P_GPIO_INT11_PEND S5P_GPIO_INT_PEND_REG(0x2c) +#define S5P_GPIO_INT12_PEND S5P_GPIO_INT_PEND_REG(0x30) +#define S5P_GPIO_INT13_PEND S5P_GPIO_INT_PEND_REG(0x34) +#define S5P_GPIO_INT14_PEND S5P_GPIO_INT_PEND_REG(0x38) +#define S5P_GPIO_INT15_PEND S5P_GPIO_INT_PEND_REG(0x3c) +#define S5P_GPIO_INT16_PEND S5P_GPIO_INT_PEND_REG(0x40) +#define S5P_GPIO_INT17_PEND S5P_GPIO_INT_PEND_REG(0x44) +#define S5P_GPIO_INT18_PEND S5P_GPIO_INT_PEND_REG(0x48) +#define S5P_GPIO_INT19_PEND S5P_GPIO_INT_PEND_REG(0x4c) +#define S5P_GPIO_INT20_PEND S5P_GPIO_INT_PEND_REG(0x50) + +#define S5P_GPIO_INT_GRPPRI S5P_GPIO_INT_PRIO_REG(0x00) +#define S5P_GPIO_INT_PRIORITY S5P_GPIO_INT_PRIO_REG(0x04) +#define S5P_GPIO_INT_SERVICE S5P_GPIO_INT_PRIO_REG(0x08) +#define S5P_GPIO_INT_SERVICE_PEND S5P_GPIO_INT_PRIO_REG(0x0c) +#define S5P_GPIO_INT_GRPFIXPRI S5P_GPIO_INT_PRIO_REG(0x10) + +#define S5P_GPIO_INT0_FIXPRI S5P_GPIO_INT_PRIO_REG(0x14) +#define S5P_GPIO_INT1_FIXPRI S5P_GPIO_INT_PRIO_REG(0x18) +#define S5P_GPIO_INT2_FIXPRI S5P_GPIO_INT_PRIO_REG(0x1c) +#define S5P_GPIO_INT3_FIXPRI S5P_GPIO_INT_PRIO_REG(0x20) +#define S5P_GPIO_INT4_FIXPRI S5P_GPIO_INT_PRIO_REG(0x24) +#define S5P_GPIO_INT5_FIXPRI S5P_GPIO_INT_PRIO_REG(0x28) +#define S5P_GPIO_INT6_FIXPRI S5P_GPIO_INT_PRIO_REG(0x2c) +#define S5P_GPIO_INT7_FIXPRI S5P_GPIO_INT_PRIO_REG(0x30) +#define S5P_GPIO_INT8_FIXPRI S5P_GPIO_INT_PRIO_REG(0x34) +#define S5P_GPIO_INT9_FIXPRI S5P_GPIO_INT_PRIO_REG(0x38) +#define S5P_GPIO_INT10_FIXPRI S5P_GPIO_INT_PRIO_REG(0x3c) +#define S5P_GPIO_INT11_FIXPRI S5P_GPIO_INT_PRIO_REG(0x40) +#define S5P_GPIO_INT12_FIXPRI S5P_GPIO_INT_PRIO_REG(0x44) +#define S5P_GPIO_INT13_FIXPRI S5P_GPIO_INT_PRIO_REG(0x48) +#define S5P_GPIO_INT14_FIXPRI S5P_GPIO_INT_PRIO_REG(0x4c) +#define S5P_GPIO_INT15_FIXPRI S5P_GPIO_INT_PRIO_REG(0x50) +#define S5P_GPIO_INT16_FIXPRI S5P_GPIO_INT_PRIO_REG(0x54) +#define S5P_GPIO_INT17_FIXPRI S5P_GPIO_INT_PRIO_REG(0x58) +#define S5P_GPIO_INT18_FIXPRI S5P_GPIO_INT_PRIO_REG(0x5c) +#define S5P_GPIO_INT19_FIXPRI S5P_GPIO_INT_PRIO_REG(0x60) +#define S5P_GPIO_INT20_FIXPRI S5P_GPIO_INT_PRIO_REG(0x64) /* GPIO H Bank Base */ #define S5P_GPIO_H0_BASE(x) (S5P_GPIO_H_REG(0x0) + (x)) @@ -720,31 +732,31 @@ #define S5P_GPIO_H0_CON S5P_GPIO_H0_BASE(CON_OFFSET) #define S5P_GPIO_H0_DAT S5P_GPIO_H0_BASE(DAT_OFFSET) -#define S5P_GPIO_H0_PULL S5P_GPIO_H0_BASE(PULL_OFFSET) +#define S5P_GPIO_H0_PULL S5P_GPIO_H0_BASE(PULL_OFFSET) #define S5P_GPIO_H0_DRV S5P_GPIO_H0_BASE(DRV_OFFSET) -#define S5P_GPIO_H0_PDNCON S5P_GPIO_H0_BASE(PDNCON_OFFSET) -#define S5P_GPIO_H0_PDNPUL S5P_GPIO_H0_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_H0_PDNCON S5P_GPIO_H0_BASE(PDNCON_OFFSET) +#define S5P_GPIO_H0_PDNPUL S5P_GPIO_H0_BASE(PDNPULL_OFFSET) #define S5P_GPIO_H1_CON S5P_GPIO_H1_BASE(CON_OFFSET) #define S5P_GPIO_H1_DAT S5P_GPIO_H1_BASE(DAT_OFFSET) -#define S5P_GPIO_H1_PULL S5P_GPIO_H1_BASE(PULL_OFFSET) +#define S5P_GPIO_H1_PULL S5P_GPIO_H1_BASE(PULL_OFFSET) #define S5P_GPIO_H1_DRV S5P_GPIO_H1_BASE(DRV_OFFSET) -#define S5P_GPIO_H1_PDNCON S5P_GPIO_H1_BASE(PDNCON_OFFSET) -#define S5P_GPIO_H1_PDNPUL S5P_GPIO_H1_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_H1_PDNCON S5P_GPIO_H1_BASE(PDNCON_OFFSET) +#define S5P_GPIO_H1_PDNPUL S5P_GPIO_H1_BASE(PDNPULL_OFFSET) #define S5P_GPIO_H2_CON S5P_GPIO_H2_BASE(CON_OFFSET) #define S5P_GPIO_H2_DAT S5P_GPIO_H2_BASE(DAT_OFFSET) -#define S5P_GPIO_H2_PULL S5P_GPIO_H2_BASE(PULL_OFFSET) +#define S5P_GPIO_H2_PULL S5P_GPIO_H2_BASE(PULL_OFFSET) #define S5P_GPIO_H2_DRV S5P_GPIO_H2_BASE(DRV_OFFSET) -#define S5P_GPIO_H2_PDNCON S5P_GPIO_H2_BASE(PDNCON_OFFSET) -#define S5P_GPIO_H2_PDNPUL S5P_GPIO_H2_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_H2_PDNCON S5P_GPIO_H2_BASE(PDNCON_OFFSET) +#define S5P_GPIO_H2_PDNPUL S5P_GPIO_H2_BASE(PDNPULL_OFFSET) #define S5P_GPIO_H3_CON S5P_GPIO_H3_BASE(CON_OFFSET) #define S5P_GPIO_H3_DAT S5P_GPIO_H3_BASE(DAT_OFFSET) -#define S5P_GPIO_H3_PULL S5P_GPIO_H3_BASE(PULL_OFFSET) +#define S5P_GPIO_H3_PULL S5P_GPIO_H3_BASE(PULL_OFFSET) #define S5P_GPIO_H3_DRV S5P_GPIO_H3_BASE(DRV_OFFSET) -#define S5P_GPIO_H3_PDNCON S5P_GPIO_H3_BASE(PDNCON_OFFSET) -#define S5P_GPIO_H3_PDNPUL S5P_GPIO_H3_BASE(PDNPULL_OFFSET) +#define S5P_GPIO_H3_PDNCON S5P_GPIO_H3_BASE(PDNCON_OFFSET) +#define S5P_GPIO_H3_PDNPUL S5P_GPIO_H3_BASE(PDNPULL_OFFSET) /* GPIO Wakeup Interrupt Configuration */ #define S5P_GPIO_WAKEUP_INT0_CON S5P_WAKEUP_INT_CON(0x00) @@ -774,26 +786,25 @@ #define S5P_GPIO_WAKEUP_INT2_PEND S5P_WAKEUP_INT_PEND(0x08) #define S5P_GPIO_WAKEUP_INT3_PEND S5P_WAKEUP_INT_PEND(0x0c) - /* * Vector Interrupt Controller * : VIC0, VIC1, VIC2 */ /* VIC0 */ -#define S5P_VIC0_BASE(x) (S5P_PA_VIC0 + (x)) +#define S5P_VIC0_BASE(x) (S5P_PA_VIC0 + (x)) #define S5P_VIC0_VECT_ADDR_BASE(x) (S5P_PA_VIC0 + 0x100 + (x)) #define S5P_VIC0_VECT_PRIO_BASE(x) (S5P_PA_VIC0 + 0x200 + (x)) #define S5P_VIC0_ADDRESS_BASE(x) (S5P_PA_VIC0 + 0xf00 + (x)) /* Vector Interrupt Offset */ -#define VIC_IRQSTATUS_OFFSET 0x0 /* IRQ Status Register */ -#define VIC_FIQSTATUS_OFFSET 0x4 /* FIQ Status Register */ -#define VIC_RAWINTR_OFFSET 0x8 /* Raw Interrupt Status Register */ -#define VIC_INTSELECT_OFFSET 0xc /* Interrupt Select Register */ +#define VIC_IRQSTATUS_OFFSET 0x0 /* IRQ Status Register */ +#define VIC_FIQSTATUS_OFFSET 0x4 /* FIQ Status Register */ +#define VIC_RAWINTR_OFFSET 0x8 /* Raw Interrupt Status Register */ +#define VIC_INTSELECT_OFFSET 0xc /* Interrupt Select Register */ #define VIC_INTENABLE_OFFSET 0x10 /* Interrupt Enable Register */ #define VIC_INTENCLEAR_OFFSET 0x14 /* Interrupt Enable Clear Register */ -#define VIC_SOFTINT_OFFSET 0x18 /* Software Interrupt Register */ +#define VIC_SOFTINT_OFFSET 0x18 /* Software Interrupt Register */ #define VIC_SOFTINTCLEAR_OFFSET 0x1c /* Software Interrupt Clear Register */ #define VIC_PROTECTION_OFFSET 0x20 /* Protection Enable Register */ #define VIC_SWPRIORITYMASK_OFFSET 0x24 /* Software Priority Mask Register */ @@ -807,10 +818,10 @@ #define S5P_VIC0INTENABLE S5P_VIC0_BASE(VIC_INTENABLE_OFFSET) #define S5P_VIC0INTENCLEAR S5P_VIC0_BASE(VIC_INTENCLEAR_OFFSET) #define S5P_VIC0SOFTINT S5P_VIC0_BASE(VIC_SOFTINT_OFFSET) -#define S5P_VIC0SOFTINTCLEAR S5P_VIC0_BASE(VIC_SOFTINTCLEAR_OFFSET) +#define S5P_VIC0SOFTINTCLEAR S5P_VIC0_BASE(VIC_SOFTINTCLEAR_OFFSET) #define S5P_VIC0PROTECTION S5P_VIC0_BASE(VIC_PROTECTION_OFFSET) -#define S5P_VIC0SWPRIORITYMASK S5P_VIC0_BASE(VIC_SWPRIORITYMASK_OFFSET) -#define S5P_VIC0PRIORITYDAISY S5P_VIC0_BASE(VIC_PRIORITYDAISY_OFFSET) +#define S5P_VIC0SWPRIORITYMASK S5P_VIC0_BASE(VIC_SWPRIORITYMASK_OFFSET) +#define S5P_VIC0PRIORITYDAISY S5P_VIC0_BASE(VIC_PRIORITYDAISY_OFFSET) #define S5P_VIC0VECTADDR0 S5P_VIC0_VECT_ADDR_BASE(0x00) #define S5P_VIC0VECTADDR1 S5P_VIC0_VECT_ADDR_BASE(0x04) @@ -888,9 +899,8 @@ #define S5P_VIC0PCELLID2 S5P_VIC0_ADDRESS_BASE(0xf8) #define S5P_VIC0PCELLID3 S5P_VIC0_ADDRESS_BASE(0xfc) - /* VIC1 */ -#define S5P_VIC1_BASE(x) (S5P_PA_VIC1 + (x)) +#define S5P_VIC1_BASE(x) (S5P_PA_VIC1 + (x)) #define S5P_VIC1_VECT_ADDR_BASE(x) (S5P_PA_VIC1 + 0x100 + (x)) #define S5P_VIC1_VECT_PRIO_BASE(x) (S5P_PA_VIC1 + 0x200 + (x)) #define S5P_VIC1_ADDRESS_BASE(x) (S5P_PA_VIC1 + 0xf00 + (x)) @@ -902,10 +912,10 @@ #define S5P_VIC1INTENABLE S5P_VIC1_BASE(VIC_INTENABLE_OFFSET) #define S5P_VIC1INTENCLEAR S5P_VIC1_BASE(VIC_INTENCLEAR_OFFSET) #define S5P_VIC1SOFTINT S5P_VIC1_BASE(VIC_SOFTINT_OFFSET) -#define S5P_VIC1SOFTINTCLEAR S5P_VIC1_BASE(VIC_SOFTINTCLEAR_OFFSET) +#define S5P_VIC1SOFTINTCLEAR S5P_VIC1_BASE(VIC_SOFTINTCLEAR_OFFSET) #define S5P_VIC1PROTECTION S5P_VIC1_BASE(VIC_PROTECTION_OFFSET) -#define S5P_VIC1SWPRIORITYMASK S5P_VIC1_BASE(VIC_SWPRIORITYMASK_OFFSET) -#define S5P_VIC1PRIORITYDAISY S5P_VIC1_BASE(VIC_PRIORITYDAISY_OFFSET) +#define S5P_VIC1SWPRIORITYMASK S5P_VIC1_BASE(VIC_SWPRIORITYMASK_OFFSET) +#define S5P_VIC1PRIORITYDAISY S5P_VIC1_BASE(VIC_PRIORITYDAISY_OFFSET) #define S5P_VIC1VECTADDR0 S5P_VIC1_VECT_ADDR_BASE(0x00) #define S5P_VIC1VECTADDR1 S5P_VIC1_VECT_ADDR_BASE(0x04) @@ -984,11 +994,10 @@ #define S5P_VIC1PCELLID3 S5P_VIC1_ADDRESS_BASE(0xfc) #define S5P_VIC1_BASE_REG __REG(S5P_VIC1_BASE(0x0)) -#define S5P_VIC1INTENABLE_REG __REG(S5P_VIC1INTENABLE) - +#define S5P_VIC1INTENABLE_REG __REG(S5P_VIC1INTENABLE) /* VIC2 */ -#define S5P_VIC2_BASE(x) (S5P_PA_VIC2 + (x)) +#define S5P_VIC2_BASE(x) (S5P_PA_VIC2 + (x)) #define S5P_VIC2_VECT_ADDR_BASE(x) (S5P_PA_VIC2 + 0x100 + (x)) #define S5P_VIC2_VECT_PRIO_BASE(x) (S5P_PA_VIC2 + 0x200 + (x)) #define S5P_VIC2_ADDRESS_BASE(x) (S5P_PA_VIC2 + 0xf00 + (x)) @@ -1000,10 +1009,10 @@ #define S5P_VIC2INTENABLE S5P_VIC2_BASE(VIC_INTENABLE_OFFSET) #define S5P_VIC2INTENCLEAR S5P_VIC2_BASE(VIC_INTENCLEAR_OFFSET) #define S5P_VIC2SOFTINT S5P_VIC2_BASE(VIC_SOFTINT_OFFSET) -#define S5P_VIC2SOFTINTCLEAR S5P_VIC2_BASE(VIC_SOFTINTCLEAR_OFFSET) +#define S5P_VIC2SOFTINTCLEAR S5P_VIC2_BASE(VIC_SOFTINTCLEAR_OFFSET) #define S5P_VIC2PROTECTION S5P_VIC2_BASE(VIC_PROTECTION_OFFSET) -#define S5P_VIC2SWPRIORITYMASK S5P_VIC2_BASE(VIC_SWPRIORITYMASK_OFFSET) -#define S5P_VIC2PRIORITYDAISY S5P_VIC2_BASE(VIC_PRIORITYDAISY_OFFSET) +#define S5P_VIC2SWPRIORITYMASK S5P_VIC2_BASE(VIC_SWPRIORITYMASK_OFFSET) +#define S5P_VIC2PRIORITYDAISY S5P_VIC2_BASE(VIC_PRIORITYDAISY_OFFSET) #define S5P_VIC2VECTADDR0 S5P_VIC2_VECT_ADDR_BASE(0x00) #define S5P_VIC2VECTADDR1 S5P_VIC2_VECT_ADDR_BASE(0x04) @@ -1081,28 +1090,25 @@ #define S5P_VIC2PCELLID2 S5P_VIC2_ADDRESS_BASE(0xf8) #define S5P_VIC2PCELLID3 S5P_VIC2_ADDRESS_BASE(0xfc) - - - /* * TrustZone Interrupt Controller * : TZI0, TZI1, TZI2 */ -#define S5P_TZIC0_BASE(x) (S5P_PA_TZIC0 + (x)) -#define S5P_TZIC1_BASE(x) (S5P_PA_TZIC1 + (x)) -#define S5P_TZIC2_BASE(x) (S5P_PA_TZIC2 + (x)) - -#define FIQSTATUS_OFFSET (0x00) /* FIQ Status Regieter */ -#define RAWINTR_OFFSET (0x04) /* Raw Interrupt Status Register */ -#define INTSELECT_OFFSET (0x08) /* Interrupt Select Register */ -#define FIQENABLE_OFFSET (0x0c) /* FIQ Enable Register */ -#define FIQENCLEAR_OFFSET (0x10) /* FIQ Enable Clear Register */ -#define FIQBYPASS_OFFSET (0x14) /* FIQ Bypass Register */ -#define FIQPROTECTION_OFFSET (0x18) /* Protection Register */ -#define FIQLOCK_OFFSET (0x1c) /* Lock Enable Register */ -#define FIQLOCKSTATUS_OFFSET (0x20) /* Lock Status Register */ -#define PERIPHID0_OFFSET (0xfe0) /* Peripheral Identification Register */ -#define PCELLID0_OFFSET (0xff0) /* PrimeCell Identification Register */ +#define S5P_TZIC0_BASE(x) (S5P_PA_TZIC0 + (x)) +#define S5P_TZIC1_BASE(x) (S5P_PA_TZIC1 + (x)) +#define S5P_TZIC2_BASE(x) (S5P_PA_TZIC2 + (x)) + +#define FIQSTATUS_OFFSET 0x00 /* FIQ Status Regieter */ +#define RAWINTR_OFFSET 0x04 /* Raw Interrupt Status Register */ +#define INTSELECT_OFFSET 0x08 /* Interrupt Select Register */ +#define FIQENABLE_OFFSET 0x0c /* FIQ Enable Register */ +#define FIQENCLEAR_OFFSET 0x10 /* FIQ Enable Clear Register */ +#define FIQBYPASS_OFFSET 0x14 /* FIQ Bypass Register */ +#define FIQPROTECTION_OFFSET 0x18 /* Protection Register */ +#define FIQLOCK_OFFSET 0x1c /* Lock Enable Register */ +#define FIQLOCKSTATUS_OFFSET 0x20 /* Lock Status Register */ +#define PERIPHID0_OFFSET 0xfe0 /* Peripheral Identification Register */ +#define PCELLID0_OFFSET 0xff0 /* PrimeCell Identification Register */ /* TZI0 */ #define S5P_TZIC0FIQSTATUS S5P_TZIC0_BASE(FIQSTATUS_OFFSET) @@ -1111,9 +1117,9 @@ #define S5P_TZIC0FIQENABLE S5P_TZIC0_BASE(FIQENABLE_OFFSET) #define S5P_TZIC0FIQENCLEAR S5P_TZIC0_BASE(FIQENCLEAR_OFFSET) #define S5P_TZIC0FIQBYPASS S5P_TZIC0_BASE(FIQBYPASS_OFFSET) -#define S5P_TZIC0FIQPROTECTION S5P_TZIC0_BASE(FIQPROTECTION_OFFSET) +#define S5P_TZIC0FIQPROTECTION S5P_TZIC0_BASE(FIQPROTECTION_OFFSET) #define S5P_TZIC0FIQLOCK S5P_TZIC0_BASE(FIQLOCKSTATUS_OFFSET) -#define S5P_TZIC0FIQLOCKSTATUS S5P_TZIC0_BASE(PCELLID0_OFFSET) +#define S5P_TZIC0FIQLOCKSTATUS S5P_TZIC0_BASE(PCELLID0_OFFSET) #define S5P_TZIC0PERIPHID0 S5P_TZIC0_BASE(PERIPHID0_OFFSET + 0x0) #define S5P_TZIC0PERIPHID1 S5P_TZIC0_BASE(PERIPHID0_OFFSET + 0x4) @@ -1132,9 +1138,9 @@ #define S5P_TZIC1FIQENABLE S5P_TZIC1_BASE(FIQENABLE_OFFSET) #define S5P_TZIC1FIQENCLEAR S5P_TZIC1_BASE(FIQENCLEAR_OFFSET) #define S5P_TZIC1FIQBYPASS S5P_TZIC1_BASE(FIQBYPASS_OFFSET) -#define S5P_TZIC1FIQPROTECTION S5P_TZIC1_BASE(FIQPROTECTION_OFFSET) +#define S5P_TZIC1FIQPROTECTION S5P_TZIC1_BASE(FIQPROTECTION_OFFSET) #define S5P_TZIC1FIQLOCK S5P_TZIC1_BASE(FIQLOCKSTATUS_OFFSET) -#define S5P_TZIC1FIQLOCKSTATUS S5P_TZIC1_BASE(PCELLID0_OFFSET) +#define S5P_TZIC1FIQLOCKSTATUS S5P_TZIC1_BASE(PCELLID0_OFFSET) #define S5P_TZIC1PERIPHID0 S5P_TZIC1_BASE(PERIPHID0_OFFSET + 0x0) #define S5P_TZIC1PERIPHID1 S5P_TZIC1_BASE(PERIPHID0_OFFSET + 0x4) @@ -1153,9 +1159,9 @@ #define S5P_TZIC2FIQENABLE S5P_TZIC2_BASE(FIQENABLE_OFFSET) #define S5P_TZIC2FIQENCLEAR S5P_TZIC2_BASE(FIQENCLEAR_OFFSET) #define S5P_TZIC2FIQBYPASS S5P_TZIC2_BASE(FIQBYPASS_OFFSET) -#define S5P_TZIC2FIQPROTECTION S5P_TZIC2_BASE(FIQPROTECTION_OFFSET) +#define S5P_TZIC2FIQPROTECTION S5P_TZIC2_BASE(FIQPROTECTION_OFFSET) #define S5P_TZIC2FIQLOCK S5P_TZIC2_BASE(FIQLOCKSTATUS_OFFSET) -#define S5P_TZIC2FIQLOCKSTATUS S5P_TZIC2_BASE(PCELLID0_OFFSET) +#define S5P_TZIC2FIQLOCKSTATUS S5P_TZIC2_BASE(PCELLID0_OFFSET) #define S5P_TZIC2PERIPHID0 S5P_TZIC2_BASE(PERIPHID0_OFFSET + 0x0) #define S5P_TZIC2PERIPHID1 S5P_TZIC2_BASE(PERIPHID0_OFFSET + 0x4) @@ -1167,8 +1173,6 @@ #define S5P_TZIC2PCELLID2 S5P_TZIC2_BASE(PCELLID2_OFFSET + 0x0) #define S5P_TZIC2PCELLID3 S5P_TZIC2_BASE(PCELLID3_OFFSET + 0x0) - - /* * Memory : SDRAM, SROM, OneNand */ @@ -1176,7 +1180,7 @@ /* DRAM Memory Controller */ #define S5P_DMC_BASE(x) (S5P_PA_DMC + (x)) -#define CONCONTROL_OFFSET 0x0 /* Controller Control Register */ +#define CONCONTROL_OFFSET 0x0 /* Controller Control Register */ #define MEMCONTROL_OFFSET 0x04 /* Memory Control Register */ #define MEMCONFIG0_OFFSET 0x08 /* Memory Chip0 Configuration Register */ #define MEMCONFIG1_OFFSET 0x0c /* Memory Chip1 Configuration Register */ @@ -1255,7 +1259,6 @@ #define S5P_QOSCONTROL7 S5P_DMC_BASE(QOSCONTROL7_OFFSET) #define S5P_QOSCONFIG7 S5P_DMC_BASE(QOSCONFIG7_OFFSET) - /* SROM Base */ #define S5P_SROMC_BASE(x) (S5P_PA_SROMC + (x)) @@ -1269,7 +1272,7 @@ #define SROM_BC5_OFFSET 0x18 /* SROM Register */ -#define S5P_SROM_BW S5P_SROMC_BASE(SROM_BW_OFFSET) +#define S5P_SROM_BW S5P_SROMC_BASE(SROM_BW_OFFSET) #define S5P_SROM_BC0 S5P_SROMC_BASE(SROM_BC0_OFFSET) #define S5P_SROM_BC1 S5P_SROMC_BASE(SROM_BC1_OFFSET) #define S5P_SROM_BC2 S5P_SROMC_BASE(SROM_BC2_OFFSET) @@ -1278,68 +1281,66 @@ #define S5P_SROM_BC5 S5P_SROMC_BASE(SROM_BC5_OFFSET) /* SROM Addressing */ -#define S5P_SROM_BW_REG __REG(S5P_SROM_BW) -#define S5P_SROM_BC0_REG __REG(S5P_SROM_BC0) -#define S5P_SROM_BC1_REG __REG(S5P_SROM_BC1) -#define S5P_SROM_BC2_REG __REG(S5P_SROM_BC2) -#define S5P_SROM_BC3_REG __REG(S5P_SROM_BC3) -#define S5P_SROM_BC4_REG __REG(S5P_SROM_BC4) -#define S5P_SROM_BC5_REG __REG(S5P_SROM_BC5) - - +#define S5P_SROM_BW_REG __REG(S5P_SROM_BW) +#define S5P_SROM_BC0_REG __REG(S5P_SROM_BC0) +#define S5P_SROM_BC1_REG __REG(S5P_SROM_BC1) +#define S5P_SROM_BC2_REG __REG(S5P_SROM_BC2) +#define S5P_SROM_BC3_REG __REG(S5P_SROM_BC3) +#define S5P_SROM_BC4_REG __REG(S5P_SROM_BC4) +#define S5P_SROM_BC5_REG __REG(S5P_SROM_BC5) /* OneNand */ #define S5P_ONENANDC_BASE(x) (S5P_PA_ONENANDC + (x)) -#define MEM_CFG_OFFSET 0x0 -#define BURST_LEN_OFFSET 0x10 -#define MEM_RESET_OFFSET 0x20 -#define INT_ERR_STAT_OFFSET 0x30 -#define INT_ERR_MASK_OFFSET 0x40 -#define INT_ERR_ACK_OFFSET 0x50 +#define MEM_CFG_OFFSET 0x0 +#define BURST_LEN_OFFSET 0x10 +#define MEM_RESET_OFFSET 0x20 +#define INT_ERR_STAT_OFFSET 0x30 +#define INT_ERR_MASK_OFFSET 0x40 +#define INT_ERR_ACK_OFFSET 0x50 #define ECC_ERR_STAT_1_OFFSET 0x60 -#define MANUFACT_ID_OFFSET 0x70 -#define DEVICE_ID_OFFSET 0x80 +#define MANUFACT_ID_OFFSET 0x70 +#define DEVICE_ID_OFFSET 0x80 #define DATA_BUF_SIZE_OFFSET 0x90 #define BOOT_BUF_SIZE_OFFSET 0xa0 -#define BUF_AMOUNT_OFFSET 0xb0 -#define TECH_OFFSET 0xc0 -#define FBA_WIDTH_OFFSET 0xd0 -#define FPA_WIDTH_OFFSET 0xe0 -#define FSA_WIDTH_OFFSET 0xf0 -#define REVISION_OFFSET 0x100 -#define SYNC_MODE_OFFSET 0x130 -#define TRANS_SPARE_OFFSET 0x140 -#define PAGE_CNT_OFFSET 0x170 +#define BUF_AMOUNT_OFFSET 0xb0 +#define TECH_OFFSET 0xc0 +#define FBA_WIDTH_OFFSET 0xd0 +#define FPA_WIDTH_OFFSET 0xe0 +#define FSA_WIDTH_OFFSET 0xf0 +#define REVISION_OFFSET 0x100 +#define SYNC_MODE_OFFSET 0x130 +#define TRANS_SPARE_OFFSET 0x140 +#define PAGE_CNT_OFFSET 0x170 #define ERR_PAGE_ADDR_OFFSET 0x180 -#define BURST_RD_LAT_OFFSET 0x190 +#define BURST_RD_LAT_OFFSET 0x190 #define INT_PIN_ENABLE_OFFSET 0x1a0 -#define INT_MON_CYC_OFFSET 0x1b0 -#define ACC_CLOCK_OFFSET 0x1c0 -#define ERR_BLK_ADDR_OFFSET 0x1e0 -#define FLASH_VER_ID_OFFSET 0x1f0 -#define BANK_EN_OFFSET 0x220 -#define WTCHDG_RST_L_OFFSET 0x260 -#define WTCHDG_RST_H_OFFSET 0x270 -#define SYNC_WRITE_OFFSET 0x280 -#define CACHE_READ_OFFSET 0x290 -#define COLD_RST_DLY_OFFSET 0x2a0 -#define DDP_DEVICE_OFFSET 0x2b0 -#define MULTI_PLANE_OFFSET 0x2c0 -#define TRANS_MODE_OFFSET 0x2e0 -#define DEV_STAT_OFFSET 0x2f0 +#define INT_MON_CYC_OFFSET 0x1b0 +#define ACC_CLOCK_OFFSET 0x1c0 +#define ERR_BLK_ADDR_OFFSET 0x1e0 +#define FLASH_VER_ID_OFFSET 0x1f0 +#define BANK_EN_OFFSET 0x220 +#define WTCHDG_RST_L_OFFSET 0x260 +#define WTCHDG_RST_H_OFFSET 0x270 +#define SYNC_WRITE_OFFSET 0x280 +#define CACHE_READ_OFFSET 0x290 +#define COLD_RST_DLY_OFFSET 0x2a0 +#define DDP_DEVICE_OFFSET 0x2b0 +#define MULTI_PLANE_OFFSET 0x2c0 +#define TRANS_MODE_OFFSET 0x2e0 +#define DEV_STAT_OFFSET 0x2f0 #define ECC_ERR_STAT_2_OFFSET 0x300 #define ECC_ERR_STAT_3_OFFSET 0x310 #define ECC_ERR_STAT_4_OFFSET 0x320 -#define EFCT_BUF_CNT_OFFSET 0x330 +#define EFCT_BUF_CNT_OFFSET 0x330 #define DEV_PAGE_SIZE_OFFSET 0x340 -#define SUPERLOAD_EN_OFFSET 0x350 -#define CACHE_PRG_EN_OFFSET 0x360 +#define SUPERLOAD_EN_OFFSET 0x350 +#define CACHE_PRG_EN_OFFSET 0x360 #define SINGLE_PAGE_BUF_OFFSET 0x370 -#define OFFSET_ADDR_OFFSET 0x380 +#define OFFSET_ADDR_OFFSET 0x380 #define INT_MON_STATUS_OFFSET 0x390 -#define S5P_MEM_CFG S5P_ONENANDC_BASE(MEM_CFG_OFFSET) +#define S5P_MEM_CFG S5P_ONENANDC_BASE(MEM_CFG_OFFSET) #define S5P_BURST_LEN S5P_ONENANDC_BASE(BURST_LEN_OFFSET) #define S5P_MEM_RESET S5P_ONENANDC_BASE(MEM_RESET_OFFSET) #define S5P_INT_ERR_STAT S5P_ONENANDC_BASE(INT_ERR_STAT_OFFSET) @@ -1351,7 +1352,7 @@ #define S5P_DATA_BUF_SIZE S5P_ONENANDC_BASE(DATA_BUF_SIZE_OFFSET) #define S5P_BOOT_BUF_SIZE S5P_ONENANDC_BASE(BOOT_BUF_SIZE_OFFSET) #define S5P_BUF_AMOUNT S5P_ONENANDC_BASE(BUF_AMOUNT_OFFSET) -#define S5P_TECH S5P_ONENANDC_BASE(TECH_OFFSET) +#define S5P_TECH S5P_ONENANDC_BASE(TECH_OFFSET) #define S5P_FBA_WIDTH S5P_ONENANDC_BASE(FBA_WIDTH_OFFSET) #define S5P_FPA_WIDTH S5P_ONENANDC_BASE(FPA_WIDTH_OFFSET) #define S5P_FSA_WIDTH S5P_ONENANDC_BASE(FSA_WIDTH_OFFSET) @@ -1366,7 +1367,7 @@ #define S5P_ACC_CLOCK S5P_ONENANDC_BASE(ACC_CLOCK_OFFSET) #define S5P_ERR_BLK_ADDR S5P_ONENANDC_BASE(ERR_BLK_ADDR_OFFSET) #define S5P_FLASH_VER_ID S5P_ONENANDC_BASE(FLASH_VER_ID_OFFSET) -#define S5P_BANK_EN S5P_ONENANDC_BASE(BANK_EN_OFFSET) +#define S5P_BANK_EN S5P_ONENANDC_BASE(BANK_EN_OFFSET) #define S5P_WTCHDG_RST_L S5P_ONENANDC_BASE(WTCHDG_RST_L_OFFSET) #define S5P_WTCHDG_RST_H S5P_ONENANDC_BASE(WTCHDG_RST_H_OFFSET) #define S5P_SYNC_WRITE S5P_ONENANDC_BASE(SYNC_WRITE_OFFSET) @@ -1374,7 +1375,7 @@ #define S5P_COLD_RST_DLY S5P_ONENANDC_BASE(COLD_RST_DLY_OFFSET) #define S5P_DDP_DEVICE S5P_ONENANDC_BASE(DDP_DEVICE_OFFSET) #define S5P_MULTI_PLANE S5P_ONENANDC_BASE(MULTI_PLANE_OFFSET) -#define S5P_MEM_CNT S5P_ONENANDC_BASE(MEM_CNT_OFFSET) +#define S5P_MEM_CNT S5P_ONENANDC_BASE(MEM_CNT_OFFSET) #define S5P_TRANS_MODE S5P_ONENANDC_BASE(TRANS_MODE_OFFSET) #define S5P_DEV_START S5P_ONENANDC_BASE(DEV_START_OFFSET) #define S5P_ECC_ERR_STAT_2 S5P_ONENANDC_BASE(ECC_ERR_STAT_2_OFFSET) @@ -1388,9 +1389,6 @@ #define S5P_OFFSET_ADDR S5P_ONENANDC_BASE(OFFSET_ADDR_OFFSET) #define S5P_INT_MON_STATUS S5P_ONENANDC_BASE(INT_MON_STATUS_OFFSET) - - - /* * Timer * : PWM, Watchdog, System timer, RTC @@ -1400,22 +1398,22 @@ #define S5P_PWMTIMER_BASE(x) (S5P_PA_PWMTIMER + (x)) /* PWM timer offset */ -#define PWM_TCFG0_OFFSET 0x0 -#define PWM_TCFG1_OFFSET 0x04 -#define PWM_TCON_OFFSET 0x08 -#define PWM_TCNTB0_OFFSET 0x0c -#define PWM_TCMPB0_OFFSET 0x10 -#define PWM_TCNTO0_OFFSET 0x14 -#define PWM_TCNTB1_OFFSET 0x18 -#define PWM_TCMPB1_OFFSET 0x1c -#define PWM_TCNTO1_OFFSET 0x20 -#define PWM_TCNTB2_OFFSET 0x24 -#define PWM_TCMPB2_OFFSET 0x28 -#define PWM_TCNTO2_OFFSET 0x2c -#define PWM_TCNTB3_OFFSET 0x30 -#define PWM_TCNTO3_OFFSET 0x38 -#define PWM_TCNTB4_OFFSET 0x3c -#define PWM_TCNTO4_OFFSET 0x40 +#define PWM_TCFG0_OFFSET 0x0 +#define PWM_TCFG1_OFFSET 0x04 +#define PWM_TCON_OFFSET 0x08 +#define PWM_TCNTB0_OFFSET 0x0c +#define PWM_TCMPB0_OFFSET 0x10 +#define PWM_TCNTO0_OFFSET 0x14 +#define PWM_TCNTB1_OFFSET 0x18 +#define PWM_TCMPB1_OFFSET 0x1c +#define PWM_TCNTO1_OFFSET 0x20 +#define PWM_TCNTB2_OFFSET 0x24 +#define PWM_TCMPB2_OFFSET 0x28 +#define PWM_TCNTO2_OFFSET 0x2c +#define PWM_TCNTB3_OFFSET 0x30 +#define PWM_TCNTO3_OFFSET 0x38 +#define PWM_TCNTB4_OFFSET 0x3c +#define PWM_TCNTO4_OFFSET 0x40 #define PWM_TINT_CSTAT_OFFSET 0x44 /* PWM timer register */ @@ -1438,42 +1436,42 @@ #define S5P_PWM_TINT_CSTAT S5P_PWMTIMER_BASE(PWM_TINT_CSTAT_OFFSET) /* PWM timer addressing */ -#define S5P_TIMER_BASE S5P_PWMTIMER_BASE(0x0) +#define S5P_TIMER_BASE S5P_PWMTIMER_BASE(0x0) #define S5P_PWMTIMER_BASE_REG __REG(S5P_PWMTIMER_BASE(0x0)) -#define S5P_PWM_TCFG0_REG __REG(S5P_PWM_TCFG0) -#define S5P_PWM_TCFG1_REG __REG(S5P_PWM_TCFG1) -#define S5P_PWM_TCON_REG __REG(S5P_PWM_TCON) -#define S5P_PWM_TCNTB0_REG __REG(S5P_PWM_TCNTB0) -#define S5P_PWM_TCMPB0_REG __REG(S5P_PWM_TCMPB0) -#define S5P_PWM_TCNTO0_REG __REG(S5P_PWM_TCNTO0) -#define S5P_PWM_TCNTB1_REG __REG(S5P_PWM_TCNTB1) -#define S5P_PWM_TCMPB1_REG __REG(S5P_PWM_TCMPB1) -#define S5P_PWM_TCNTO1_REG __REG(S5P_PWM_TCNTO1) -#define S5P_PWM_TCNTB2_REG __REG(S5P_PWM_TCNTB2) -#define S5P_PWM_TCMPB2_REG __REG(S5P_PWM_TCMPB2) -#define S5P_PWM_TCNTO2_REG __REG(S5P_PWM_TCNTO2) -#define S5P_PWM_TCNTB3_REG __REG(S5P_PWM_TCNTB3) -#define S5P_PWM_TCNTO3_REG __REG(S5P_PWM_TCNTO3) -#define S5P_PWM_TCNTB4_REG __REG(S5P_PWM_TCNTB4) -#define S5P_PWM_TCNTO4_REG __REG(S5P_PWM_TCNTO4) +#define S5P_PWM_TCFG0_REG __REG(S5P_PWM_TCFG0) +#define S5P_PWM_TCFG1_REG __REG(S5P_PWM_TCFG1) +#define S5P_PWM_TCON_REG __REG(S5P_PWM_TCON) +#define S5P_PWM_TCNTB0_REG __REG(S5P_PWM_TCNTB0) +#define S5P_PWM_TCMPB0_REG __REG(S5P_PWM_TCMPB0) +#define S5P_PWM_TCNTO0_REG __REG(S5P_PWM_TCNTO0) +#define S5P_PWM_TCNTB1_REG __REG(S5P_PWM_TCNTB1) +#define S5P_PWM_TCMPB1_REG __REG(S5P_PWM_TCMPB1) +#define S5P_PWM_TCNTO1_REG __REG(S5P_PWM_TCNTO1) +#define S5P_PWM_TCNTB2_REG __REG(S5P_PWM_TCNTB2) +#define S5P_PWM_TCMPB2_REG __REG(S5P_PWM_TCMPB2) +#define S5P_PWM_TCNTO2_REG __REG(S5P_PWM_TCNTO2) +#define S5P_PWM_TCNTB3_REG __REG(S5P_PWM_TCNTB3) +#define S5P_PWM_TCNTO3_REG __REG(S5P_PWM_TCNTO3) +#define S5P_PWM_TCNTB4_REG __REG(S5P_PWM_TCNTB4) +#define S5P_PWM_TCNTO4_REG __REG(S5P_PWM_TCNTO4) #define S5P_PWM_TINT_CSTAT_REG __REG(S5P_PWM_TINT_CSTAT) /* PWM timer value */ #define S5P_TCON4_AUTO_RELOAD (1 << 22) /* Interval mode(Auto Reload) of PWM Timer 4 */ -#define S5P_TCON4_UPDATE (1 << 21) /* Update TCNTB4 */ -#define S5P_TCON4_ON (1 << 20) /* start bit of PWM Timer 4 */ +#define S5P_TCON4_UPDATE (1 << 21) /* Update TCNTB4 */ +#define S5P_TCON4_ON (1 << 20) /* start bit of PWM Timer 4 */ /* System Timer */ #define S5P_SYSTIMER_BASE(x) (S5P_PA_SYSTEM + (x)) -#define SYS_TCFG_OFFSET 0x0 -#define SYS_TCON_OFFSET 0x04 -#define SYS_TCNTB_OFFSET 0x08 -#define SYS_TCNTO_OFFSET 0x0c -#define SYS_ICNTB_OFFSET 0x10 -#define SYS_ICNTO_OFFSET 0x14 +#define SYS_TCFG_OFFSET 0x0 +#define SYS_TCON_OFFSET 0x04 +#define SYS_TCNTB_OFFSET 0x08 +#define SYS_TCNTO_OFFSET 0x0c +#define SYS_ICNTB_OFFSET 0x10 +#define SYS_ICNTO_OFFSET 0x14 #define SYS_INT_CSTAT_OFFSET 0x18 #define S5P_SYS_TCFG S5P_SYSTIMER_BASE(SYS_TCFG_OFFSET) @@ -1493,16 +1491,15 @@ #define WTCNT_OFFSET 0x8 #define WTCLRINT_OFFSET 0xc -#define S5P_WTCON S5P_WATCHDOG_BASE(WTCON_OFFSET) -#define S5P_WTDAT S5P_WATCHDOG_BASE(WTDAT_OFFSET) -#define S5P_WTCNT S5P_WATCHDOG_BASE(WTCNT_OFFSET) +#define S5P_WTCON S5P_WATCHDOG_BASE(WTCON_OFFSET) +#define S5P_WTDAT S5P_WATCHDOG_BASE(WTDAT_OFFSET) +#define S5P_WTCNT S5P_WATCHDOG_BASE(WTCNT_OFFSET) #define S5P_WTCLRINT S5P_WATCHDOG_BASE(WTCLRINT_OFFSET) - /* RTC */ -#define S5P_RTC_BASE(x) (S5P_PA_RTC + (x)) +#define S5P_RTC_BASE(x) (S5P_PA_RTC + (x)) -#define INTP_OFFSET 0x30 +#define INTP_OFFSET 0x30 #define RTCCON_OFFSET 0x40 #define TICCNT_OFFSET 0x44 #define RTCALM_OFFSET 0x50 @@ -1522,41 +1519,37 @@ #define BCDMON_OFFSET 0x84 #define BCDYEAR_OFFSET 0x88 -#define CURTICCNT 0x90 - - +#define CURTICCNT 0x90 +#define S5P_INTP S5P_RTC_BASE(INTP_OFFSET) +#define S5P_RTCCON S5P_RTC_BASE(RTCCON_OFFSET) +#define S5P_TICCNT S5P_RTC_BASE(TICCNT_OFFSET) +#define S5P_RTCALM S5P_RTC_BASE(RTCALM_OFFSET) -#define S5P_INTP S5P_RTC_BASE(INTP_OFFSET) -#define S5P_RTCCON S5P_RTC_BASE(RTCCON_OFFSET) -#define S5P_TICCNT S5P_RTC_BASE(TICCNT_OFFSET) -#define S5P_RTCALM S5P_RTC_BASE(RTCALM_OFFSET) +#define S5P_ALMSEC S5P_RTC_BASE(ALMSEC_OFFSET) +#define S5P_ALMMIN S5P_RTC_BASE(ALMMIN_OFFSET) +#define S5P_ALMHOUR S5P_RTC_BASE(ALMHOUR_OFFSET) +#define S5P_ALMDATE S5P_RTC_BASE(ALMDATE_OFFSET) +#define S5P_ALMMON S5P_RTC_BASE(ALMMON_OFFSET) +#define S5P_ALMYEAR S5P_RTC_BASE(ALMYEAR_OFFSET) -#define S5P_ALMSEC S5P_RTC_BASE(ALMSEC_OFFSET) -#define S5P_ALMMIN S5P_RTC_BASE(ALMMIN_OFFSET) -#define S5P_ALMHOUR S5P_RTC_BASE(ALMHOUR_OFFSET) -#define S5P_ALMDATE S5P_RTC_BASE(ALMDATE_OFFSET) -#define S5P_ALMMON S5P_RTC_BASE(ALMMON_OFFSET) -#define S5P_ALMYEAR S5P_RTC_BASE(ALMYEAR_OFFSET) - -#define S5P_BCDSEC S5P_RTC_BASE(BCDSEC_OFFSET) -#define S5P_BCDMIN S5P_RTC_BASE(BCDMIN_OFFSET) -#define S5P_BCDHOUR S5P_RTC_BASE(BCDHOUR_OFFSET) -#define S5P_BCDDATE S5P_RTC_BASE(BCDDATE_OFFSET) -#define S5P_BCDDAY S5P_RTC_BASE(BCDDAY_OFFSET) -#define S5P_BCDMON S5P_RTC_BASE(BCDMON_OFFSET) -#define S5P_BCDYEAR S5P_RTC_BASE(BCDYEAR_OFFSET) +#define S5P_BCDSEC S5P_RTC_BASE(BCDSEC_OFFSET) +#define S5P_BCDMIN S5P_RTC_BASE(BCDMIN_OFFSET) +#define S5P_BCDHOUR S5P_RTC_BASE(BCDHOUR_OFFSET) +#define S5P_BCDDATE S5P_RTC_BASE(BCDDATE_OFFSET) +#define S5P_BCDDAY S5P_RTC_BASE(BCDDAY_OFFSET) +#define S5P_BCDMON S5P_RTC_BASE(BCDMON_OFFSET) +#define S5P_BCDYEAR S5P_RTC_BASE(BCDYEAR_OFFSET) #define S5P_CURTICCNT S5P_RTC_BASE(CURTICCNT_OFFSET) - /* * UART */ #define S5P_PA_UART S5P_ADDR(0x0c000000) /* UART */ -#define UARTx_OFFSET(x) (S5P_PA_UART + x * 0x400) +#define UARTx_OFFSET(x) (S5P_PA_UART + x * 0x400) -#define S5P_UART_BASE (S5P_PA_UART) +#define S5P_UART_BASE (S5P_PA_UART) #define ULCON_OFFSET 0x00 #define UCON_OFFSET 0x04 @@ -1596,8 +1589,4 @@ static inline s5pc1xx_uart *s5pc1xx_get_base_uart(enum s5pc1xx_uarts_nr nr) } #endif - - #endif /*__S5PC100_H__*/ - - -- 2.7.4