From c362f42b6acc8f159ac7453f370cf72a672cbc12 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 8 Apr 2018 17:53:15 +0000 Subject: [PATCH] [X86][Znver1] Remove InstRWs for BLENDVPS/PD Summary: This removes the InstRWs for BLENDVPS/PD in favor of WriteFVarBlend. The latency listed was 3 cycles but WriteFVarBlend is defined as 1 cycle latency. The 1 cycle latency matches Agner Fog's data. The patterns were missing the VEX forms which is why there are no test changes. We don't test "-mcpu=znver1 -mattr=-avx" Reviewers: RKSimon, GGanesh Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44841 llvm-svn: 329538 --- llvm/lib/Target/X86/X86ScheduleZnver1.td | 12 ------------ llvm/test/CodeGen/X86/sse41-schedule.ll | 8 ++++---- 2 files changed, 4 insertions(+), 16 deletions(-) diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td index ccdf23f..834a254 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -1150,18 +1150,6 @@ def : InstRW<[ZnWritePShiftY], (instregex "(V?)PS(R|L)LDQYri")>; def : InstRW<[WriteMicrocoded], (instregex "VPERM2F128rr")>; def : InstRW<[WriteMicrocoded], (instregex "VPERM2F128rm")>; -// BLENDVP S/D. -def ZnWriteFPU01Lat3 : SchedWriteRes<[ZnFPU013]> { - let Latency = 3; -} -def ZnWriteFPU01Lat3Ld : SchedWriteRes<[ZnAGU, ZnFPU013]> { - let Latency = 11; - let NumMicroOps = 2; - let ResourceCycles = [1, 2]; -} -def : InstRW<[ZnWriteFPU01Lat3], (instregex "BLENDVP(S|D)rr0")>; -def : InstRW<[ZnWriteFPU01Lat3Ld, ReadAfterLd], (instregex "BLENDVP(S|D)rm0")>; - def ZnWriteBROADCAST : SchedWriteRes<[ZnAGU, ZnFPU13]> { let NumMicroOps = 2; let Latency = 8; diff --git a/llvm/test/CodeGen/X86/sse41-schedule.ll b/llvm/test/CodeGen/X86/sse41-schedule.ll index 013eb83..39052ba 100644 --- a/llvm/test/CodeGen/X86/sse41-schedule.ll +++ b/llvm/test/CodeGen/X86/sse41-schedule.ll @@ -369,8 +369,8 @@ define <2 x double> @test_blendvpd(<2 x double> %a0, <2 x double> %a1, <2 x doub ; ZNVER1-SSE: # %bb.0: ; ZNVER1-SSE-NEXT: movapd %xmm0, %xmm3 # sched: [1:0.25] ; ZNVER1-SSE-NEXT: movaps %xmm2, %xmm0 # sched: [1:0.25] -; ZNVER1-SSE-NEXT: blendvpd %xmm0, %xmm1, %xmm3 # sched: [3:0.33] -; ZNVER1-SSE-NEXT: blendvpd %xmm0, (%rdi), %xmm3 # sched: [11:0.67] +; ZNVER1-SSE-NEXT: blendvpd %xmm0, %xmm1, %xmm3 # sched: [1:0.50] +; ZNVER1-SSE-NEXT: blendvpd %xmm0, (%rdi), %xmm3 # sched: [8:0.50] ; ZNVER1-SSE-NEXT: movapd %xmm3, %xmm0 # sched: [1:0.25] ; ZNVER1-SSE-NEXT: retq # sched: [1:0.50] ; @@ -499,8 +499,8 @@ define <4 x float> @test_blendvps(<4 x float> %a0, <4 x float> %a1, <4 x float> ; ZNVER1-SSE: # %bb.0: ; ZNVER1-SSE-NEXT: movaps %xmm0, %xmm3 # sched: [1:0.25] ; ZNVER1-SSE-NEXT: movaps %xmm2, %xmm0 # sched: [1:0.25] -; ZNVER1-SSE-NEXT: blendvps %xmm0, %xmm1, %xmm3 # sched: [3:0.33] -; ZNVER1-SSE-NEXT: blendvps %xmm0, (%rdi), %xmm3 # sched: [11:0.67] +; ZNVER1-SSE-NEXT: blendvps %xmm0, %xmm1, %xmm3 # sched: [1:0.50] +; ZNVER1-SSE-NEXT: blendvps %xmm0, (%rdi), %xmm3 # sched: [8:0.50] ; ZNVER1-SSE-NEXT: movaps %xmm3, %xmm0 # sched: [1:0.25] ; ZNVER1-SSE-NEXT: retq # sched: [1:0.50] ; -- 2.7.4