From c328638b3b2e156ca53c904bff0c15b1a649c54f Mon Sep 17 00:00:00 2001 From: Jordan Justen Date: Mon, 25 May 2020 02:51:36 -0700 Subject: [PATCH] anv: Use correct CCS0 aux-map register offset in pipe flush According to Bspec, COMPCS0_CCS_AUX_INV register offset is 042C8h and COMPCS0_AUX_TABLE_BASE_ADDR is defined to 042C0h. Signed-off-by: Jordan Justen Reviewed-by: Lionel Landwerlin Reviewed-by: Sagar Ghuge Part-of: --- src/intel/vulkan/genX_cmd_buffer.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index c4ef46f..d7a129a 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1672,7 +1672,7 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch, #if GFX_VER == 12 if ((bits & ANV_PIPE_AUX_TABLE_INVALIDATE_BIT) && device->info->has_aux_map) { uint64_t register_addr = - current_pipeline == GPGPU ? GENX(CCS_CCS_AUX_INV_num) : + current_pipeline == GPGPU ? GENX(COMPCS0_CCS_AUX_INV_num) : GENX(GFX_CCS_AUX_INV_num); anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { lri.RegisterOffset = register_addr; @@ -1692,6 +1692,8 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch, anv_address_from_u64(register_addr); } } +#else + assert(!device->info->has_aux_map); #endif bits &= ~ANV_PIPE_INVALIDATE_BITS; -- 2.7.4