From c2f8c98d56f8bfa12ce34be2b38ebc093be91d75 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Sun, 23 May 2021 10:46:07 -0700 Subject: [PATCH] freedreno/registers: Add a few a6xx regs and notes A few things I noticed while playing with the emulator. Signed-off-by: Rob Clark Part-of: --- src/freedreno/.gitlab-ci/reference/crash.log | 22 +++++----- src/freedreno/registers/adreno/a6xx.xml | 28 ++++++++++++- .../registers/adreno/adreno_control_regs.xml | 49 +++++++++++++++++++++- 3 files changed, 85 insertions(+), 14 deletions(-) diff --git a/src/freedreno/.gitlab-ci/reference/crash.log b/src/freedreno/.gitlab-ci/reference/crash.log index fe1ef58..bf9eba4 100644 --- a/src/freedreno/.gitlab-ci/reference/crash.log +++ b/src/freedreno/.gitlab-ci/reference/crash.log @@ -634,8 +634,8 @@ registers: 00000000 CP_PROTECT_STATUS: 0 00000707 0x826: 00000707 00000001 0x827: 00000001 - 00009000 CP_SQE_INSTR_BASE_LO: 0x9000 - 00010000 CP_SQE_INSTR_BASE_HI: 0x10000 + 00009000 CP_SQE_INSTR_BASE: 0x9000 + 00010000 CP_SQE_INSTR_BASE+0x1: 0x10000 00000000 0x832: 00000000 00000000 0x833: 00000000 00000000 CP_MISC_CNTL: 0 @@ -1125,16 +1125,16 @@ registers: 00180000 PC_DBG_ECO_CNTL: 0x180000 00000001 PC_ADDR_MODE_CNTL: ADDR_64B 00000000 0x9e03: 00000000 - 00000000 0x9e04: 00000000 - 00000000 0x9e05: 00000000 - 00000000 0x9e06: 00000000 - 00000000 0x9e07: 00000000 + 00000000 PC_DRAW_INDX_BASE: 0 + 00000000 PC_DRAW_INDX_BASE+0x1: 0 + 00000000 PC_DRAW_FIRST_INDX: 0 + 00000000 PC_DRAW_MAX_INDICES: 0 00000000 PC_TESSFACTOR_ADDR: 0 00000000 PC_TESSFACTOR_ADDR_HI: 0 00000001 0x9e0a: 00000001 - 00004080 0x9e0b: 00004080 - 00000000 0x9e0c: 00000000 - 00000003 0x9e0d: 00000003 + 00004080 PC_DRAW_INITIATOR: { PRIM_TYPE = DI_PT_NONE | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_8_BIT | PATCH_TYPE = TESS_QUADS | 0x4000 } + 00000000 PC_DRAW_NUM_INSTANCES: 0 + 00000003 PC_DRAW_NUM_INDICES: 3 00000000 0x9e0e: 00000000 00010000 PC_VSTREAM_CONTROL: { VSC_SIZE = 1 | VSC_N = 0 } 00000000 PC_BIN_PRIM_STRM: 0 @@ -1143,7 +1143,7 @@ registers: 00000000 PC_BIN_DRAW_STRM_HI: 0 00000000 0x9e16: 00000000 00000000 0x9e19: 00000000 - 00000000 0x9e1c: 00000000 + 00000000 PC_VISIBILITY_OVERRIDE: { 0 } 00000000 0x9e20: 00000000 00000000 0x9e21: 00000000 00000000 0x9e22: 00000000 @@ -2993,7 +2993,7 @@ indexed-registers: 00000000 0x127: 00000000 00000000 0x128: 00000000 00000000 0x129: 00000000 - 00000101 0x12a: 00000101 + 00000101 MARKER: 0x101 00000004 MODE_BITMASK: 0x4 00000000 0x12c: 00000000 00000000 0x12d: 00000000 diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml index 43eb469..67e78bd 100644 --- a/src/freedreno/registers/adreno/a6xx.xml +++ b/src/freedreno/registers/adreno/a6xx.xml @@ -978,8 +978,7 @@ to upconvert to 32b float internally? - - + @@ -1095,6 +1094,7 @@ to upconvert to 32b float internally? + @@ -2492,6 +2492,13 @@ to upconvert to 32b float internally? + + + @@ -2580,8 +2587,20 @@ to upconvert to 32b float internally? + + + + + + Possibly not really "initiating" the draw but the layout is similar + to VGT_DRAW_INITIATOR on older gens + + + + + @@ -2591,6 +2610,11 @@ to upconvert to 32b float internally? + + Written by CP_SET_VISIBILITY_OVERRIDE handler + + + diff --git a/src/freedreno/registers/adreno/adreno_control_regs.xml b/src/freedreno/registers/adreno/adreno_control_regs.xml index ed7c86b..24ce699 100644 --- a/src/freedreno/registers/adreno/adreno_control_regs.xml +++ b/src/freedreno/registers/adreno/adreno_control_regs.xml @@ -43,6 +43,17 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> Writing to this triggers a register write and auto-increments REG_WRITE_ADDR. + + Note that there seems to be some upper bits that are possilby + flags, ie: + + l284: 0d12: 8a8c0003 mov $0c, 0x0003 << 20 + GPR: $0c: 00300000 + 0d13: 318c9e0b or $0c, $0c, 0x9e0b + GPR: $0c: 00309e0b + 0d14: a80c0024 cwrite $0c, [$00 + @REG_WRITE_ADDR], 0x0 + CTRL: @REG_WRITE_ADDR: 00309e0b + @@ -62,7 +73,38 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> - + + + SQE writes DRAW_STATE_SEL to select the SDS state group, and + then reads out the SDS header (DRAW_STATE_HDR), ie. the first + dword in the state group entry (see CP_SET_DRAW_STATE), and + base address of the state group cmdstream (DRAW_STATE_BASE) + + + + + base address for executing draw state group when IB_LEVEL + is set to 3 (ie. it's a bit like IB3 equiv of IBn_BASE) + + Note that SDS_BASE/SDS_DWORDS seem to be per-state-group, + the values reflected switch when DRAW_STATE_SEL is written. + + + + + state group equiv of IBn_DWORDS + + + + + + + Contains information from the first dword of the state group + entry in CP_SET_DRAW_STATE, but format isn't exactly the + same. The # of dwords is in low 16b, and mode mask is in + high 16 bits + + @@ -113,6 +155,11 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> + Seems to be a shadow for PC_MARKER + + + + Set by SET_MARKER, used to conditionally execute CP_COND_REG_EXEC and draw states. -- 2.7.4