From c2eb9e7f02118764969c49879c458c9462ccabdc Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Sat, 7 Dec 2013 14:08:52 +0100 Subject: [PATCH] pinctrl: at91: correct a few typos Signed-off-by: Alexandre Belloni Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-at91.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index a7549c4..6446dc8 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -118,7 +118,7 @@ struct at91_pin_group { }; /** - * struct at91_pinctrl_mux_ops - describes an At91 mux ops group + * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group * on new IP with support for periph C and D the way to mux in * periph A and B has changed * So provide the right call back @@ -1396,7 +1396,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) chained_irq_enter(chip, desc); for (;;) { /* Reading ISR acks pending (edge triggered) GPIO interrupts. - * When there none are pending, we're finished unless we need + * When there are none pending, we're finished unless we need * to process multiple banks (like ID_PIOCDE on sam9263). */ isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR); @@ -1505,7 +1505,7 @@ static int at91_gpio_of_irq_setup(struct device_node *node, prev = gpio_chips[at91_gpio->pioc_idx - 1]; /* The top level handler handles one bank of GPIOs, except - * on some SoC it can handles up to three... + * on some SoC it can handle up to three... * We only set up the handler for the first of the list. */ if (prev && prev->next == at91_gpio) -- 2.7.4