From c2e27ac1ce3e3141f9cf0c4f6982cd56347bc323 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Wed, 3 Jun 2020 19:41:56 +0100
Subject: [PATCH] [VectorCombine] Add multi-use shl test for D80885

---
 .../VectorCombine/X86/insert-binop-with-constant.ll       | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/llvm/test/Transforms/VectorCombine/X86/insert-binop-with-constant.ll b/llvm/test/Transforms/VectorCombine/X86/insert-binop-with-constant.ll
index 10c4971..e0d4623 100644
--- a/llvm/test/Transforms/VectorCombine/X86/insert-binop-with-constant.ll
+++ b/llvm/test/Transforms/VectorCombine/X86/insert-binop-with-constant.ll
@@ -155,6 +155,21 @@ define <2 x i64> @shl_constant_op0_load(i64* %p) {
   ret <2 x i64> %bo
 }
 
+define <4 x i32> @shl_constant_op0_multiuse(i32 %a0, <4 x i32> %a1) {
+; CHECK-LABEL: @shl_constant_op0_multiuse(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <4 x i32> <i32 undef, i32 1, i32 2, i32 3>, i32 [[A0:%.*]], i32 0
+; CHECK-NEXT:    [[MUL:%.*]] = shl <4 x i32> [[INS]], <i32 3, i32 4, i32 5, i32 6>
+; CHECK-NEXT:    [[AND:%.*]] = and <4 x i32> [[INS]], [[A1:%.*]]
+; CHECK-NEXT:    [[XOR:%.*]] = xor <4 x i32> [[AND]], [[MUL]]
+; CHECK-NEXT:    ret <4 x i32> [[XOR]]
+;
+  %ins = insertelement <4 x i32> <i32 undef, i32 1, i32 2, i32 3>, i32 %a0, i32 0
+  %mul = shl <4 x i32> %ins, <i32 3, i32 4, i32 5, i32 6>
+  %and = and <4 x i32> %ins, %a1
+  %xor = xor <4 x i32> %and, %mul
+  ret <4 x i32> %xor
+}
+
 define <2 x i64> @shl_constant_op1(i64 %x) {
 ; CHECK-LABEL: @shl_constant_op1(
 ; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i64> undef, i64 [[X:%.*]], i32 0
-- 
2.7.4