From c2d4fe51bb4f98870a2358a32809f849b0751d7c Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Tue, 12 Oct 2021 16:18:51 -0700 Subject: [PATCH] [X86] Remove little support we had for MPX GCC 9.1 removed Intel MPX support. Linux kernel removed MPX in 2019. glibc 2.35 will remove MPX. Our support is limited: we support assembling of bndmov but not bnd. Just remove it. Reviewed By: pengfei, skan Differential Revision: https://reviews.llvm.org/D111517 --- clang/test/CodeGen/ms-inline-asm.c | 11 ---- .../Target/X86/Disassembler/X86Disassembler.cpp | 4 -- .../X86/Disassembler/X86DisassemblerDecoder.h | 7 -- llvm/lib/Target/X86/X86InstrInfo.cpp | 6 -- llvm/lib/Target/X86/X86InstrInfo.td | 3 - llvm/lib/Target/X86/X86InstrMPX.td | 77 ---------------------- llvm/lib/Target/X86/X86RegisterInfo.td | 9 --- llvm/test/CodeGen/X86/ipra-reg-usage.ll | 2 +- llvm/test/MC/X86/mpx-encodings.s | 41 ------------ .../llvm-exegesis/X86/SnippetGeneratorTest.cpp | 20 ------ 10 files changed, 1 insertion(+), 179 deletions(-) delete mode 100644 llvm/lib/Target/X86/X86InstrMPX.td delete mode 100644 llvm/test/MC/X86/mpx-encodings.s diff --git a/clang/test/CodeGen/ms-inline-asm.c b/clang/test/CodeGen/ms-inline-asm.c index d1e3552..ef0345b 100644 --- a/clang/test/CodeGen/ms-inline-asm.c +++ b/clang/test/CodeGen/ms-inline-asm.c @@ -675,17 +675,6 @@ void t46() { // CHECK: call void asm sideeffect inteldialect "add eax, [eax + $$-128]", "~{eax},~{flags},~{dirflag},~{fpsr},~{flags}"() } -void t47() { - // CHECK-LABEL: define{{.*}} void @t47 - __asm { - bndmk bnd0, dword ptr [eax] - bndmk bnd1, dword ptr [ebx] - bndmk bnd2, dword ptr [ecx] - bndmk bnd3, dword ptr [edx] - } - // CHECK: call void asm sideeffect inteldialect "bndmk bnd0, dword ptr [eax]\0A\09bndmk bnd1, dword ptr [ebx]\0A\09bndmk bnd2, dword ptr [ecx]\0A\09bndmk bnd3, dword ptr [edx]", "~{bnd0},~{bnd1},~{bnd2},~{bnd3},~{dirflag},~{fpsr},~{flags}"() -} - void dot_operator(){ // CHECK-LABEL: define{{.*}} void @dot_operator __asm { mov eax, 3[ebx]A.b} diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp index 45d32de..908eb6d 100644 --- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -806,10 +806,6 @@ static int readModRM(struct InternalInstruction *insn) { return prefix##_DR0 + index; \ case TYPE_CONTROLREG: \ return prefix##_CR0 + index; \ - case TYPE_BNDR: \ - if (index > 3) \ - *valid = 0; \ - return prefix##_BND0 + index; \ case TYPE_MVSIBX: \ return prefix##_XMM0 + index; \ case TYPE_MVSIBY: \ diff --git a/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h b/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h index 4346f4c..95d3c8e 100644 --- a/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h +++ b/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h @@ -374,12 +374,6 @@ namespace X86Disassembler { ENTRY(CR14) \ ENTRY(CR15) -#define REGS_BOUND \ - ENTRY(BND0) \ - ENTRY(BND1) \ - ENTRY(BND2) \ - ENTRY(BND3) - #undef REGS_TMM #define REGS_TMM \ ENTRY(TMM0) \ @@ -414,7 +408,6 @@ namespace X86Disassembler { REGS_SEGMENT \ REGS_DEBUG \ REGS_CONTROL \ - REGS_BOUND \ REGS_TMM \ ENTRY(RIP) diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index e06202d..3526955 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -3718,12 +3718,6 @@ static unsigned getLoadStoreRegOpcode(Register Reg, HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr); } - if (X86::BNDRRegClass.hasSubClassEq(RC)) { - if (STI.is64Bit()) - return load ? X86::BNDMOV64rm : X86::BNDMOV64mr; - else - return load ? X86::BNDMOV32rm : X86::BNDMOV32mr; - } llvm_unreachable("Unknown 16-byte regclass"); } case 32: diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index 64bc3e9..6a619af 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -3159,9 +3159,6 @@ include "X86InstrAVX512.td" include "X86InstrMMX.td" include "X86Instr3DNow.td" -// MPX instructions -include "X86InstrMPX.td" - include "X86InstrVMX.td" include "X86InstrSVM.td" include "X86InstrSNP.td" diff --git a/llvm/lib/Target/X86/X86InstrMPX.td b/llvm/lib/Target/X86/X86InstrMPX.td deleted file mode 100644 index 44ba071..0000000 --- a/llvm/lib/Target/X86/X86InstrMPX.td +++ /dev/null @@ -1,77 +0,0 @@ -//===-- X86InstrMPX.td - MPX Instruction Set ---------*- tablegen -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file describes the X86 MPX instruction set, defining the -// instructions, and properties of the instructions which are needed for code -// generation, machine code emission, and analysis. -// -//===----------------------------------------------------------------------===// - -// FIXME: Investigate a better scheduler class if MPX is ever used inside LLVM. -let SchedRW = [WriteSystem] in { - -multiclass mpx_bound_make opc, string OpcodeStr> { - def 32rm: I, - Requires<[Not64BitMode]>; - def 64rm: I, - Requires<[In64BitMode]>; -} - -defm BNDMK : mpx_bound_make<0x1B, "bndmk">, XS; - -multiclass mpx_bound_check opc, string OpcodeStr> { - def 32rm: I, - Requires<[Not64BitMode]>; - def 64rm: I, - Requires<[In64BitMode]>; - - def 32rr: I, - Requires<[Not64BitMode]>; - def 64rr: I, - Requires<[In64BitMode]>; -} -defm BNDCL : mpx_bound_check<0x1A, "bndcl">, XS, NotMemoryFoldable; -defm BNDCU : mpx_bound_check<0x1A, "bndcu">, XD, NotMemoryFoldable; -defm BNDCN : mpx_bound_check<0x1B, "bndcn">, XD, NotMemoryFoldable; - -def BNDMOVrr : I<0x1A, MRMSrcReg, (outs BNDR:$dst), (ins BNDR:$src), - "bndmov\t{$src, $dst|$dst, $src}", []>, PD, - NotMemoryFoldable; -let mayLoad = 1 in { -def BNDMOV32rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src), - "bndmov\t{$src, $dst|$dst, $src}", []>, PD, - Requires<[Not64BitMode]>, NotMemoryFoldable; -def BNDMOV64rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i128mem:$src), - "bndmov\t{$src, $dst|$dst, $src}", []>, PD, - Requires<[In64BitMode]>, NotMemoryFoldable; -} -let isCodeGenOnly = 1, ForceDisassemble = 1 in -def BNDMOVrr_REV : I<0x1B, MRMDestReg, (outs BNDR:$dst), (ins BNDR:$src), - "bndmov\t{$src, $dst|$dst, $src}", []>, PD, - NotMemoryFoldable; -let mayStore = 1 in { -def BNDMOV32mr : I<0x1B, MRMDestMem, (outs), (ins i64mem:$dst, BNDR:$src), - "bndmov\t{$src, $dst|$dst, $src}", []>, PD, - Requires<[Not64BitMode]>, NotMemoryFoldable; -def BNDMOV64mr : I<0x1B, MRMDestMem, (outs), (ins i128mem:$dst, BNDR:$src), - "bndmov\t{$src, $dst|$dst, $src}", []>, PD, - Requires<[In64BitMode]>, NotMemoryFoldable; - -def BNDSTXmr: I<0x1B, MRMDestMem, (outs), (ins anymem:$dst, BNDR:$src), - "bndstx\t{$src, $dst|$dst, $src}", []>, PS; -} -let mayLoad = 1 in -def BNDLDXrm: I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src), - "bndldx\t{$src, $dst|$dst, $src}", []>, PS; -} // SchedRW diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td index ad15a54..d835f45 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.td +++ b/llvm/lib/Target/X86/X86RegisterInfo.td @@ -373,12 +373,6 @@ def CR15 : X86Reg<"cr15", 15>; def EIZ : X86Reg<"eiz", 4>; def RIZ : X86Reg<"riz", 4>; -// Bound registers, used in MPX instructions -def BND0 : X86Reg<"bnd0", 0>; -def BND1 : X86Reg<"bnd1", 1>; -def BND2 : X86Reg<"bnd2", 2>; -def BND3 : X86Reg<"bnd3", 3>; - // CET registers - Shadow Stack Pointer def SSP : X86Reg<"ssp", 0>; @@ -640,9 +634,6 @@ def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)> {let Size = 16;} def VK32WM : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;} def VK64WM : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;} -// Bound registers -def BNDR : RegisterClass<"X86", [v2i64], 128, (sequence "BND%u", 0, 3)>; - // Tiles let CopyCost = -1 in // Don't allow copying of tile registers def TILE : RegisterClass<"X86", [x86amx], 8192, diff --git a/llvm/test/CodeGen/X86/ipra-reg-usage.ll b/llvm/test/CodeGen/X86/ipra-reg-usage.ll index 51a61aa..c2b6e69 100644 --- a/llvm/test/CodeGen/X86/ipra-reg-usage.ll +++ b/llvm/test/CodeGen/X86/ipra-reg-usage.ll @@ -3,7 +3,7 @@ target triple = "x86_64-unknown-unknown" declare void @bar1() define preserve_allcc void @foo()#0 { -; CHECK: foo Clobbered Registers: $cs $df $ds $eflags $eip $eiz $es $esp $fpcw $fpsw $fs $gs $hip $hsp $ip $mxcsr $rip $riz $rsp $sp $sph $spl $ss $ssp $tmmcfg $bnd0 $bnd1 $bnd2 $bnd3 $cr0 $cr1 $cr2 $cr3 $cr4 $cr5 $cr6 $cr7 $cr8 $cr9 $cr10 $cr11 $cr12 $cr13 $cr14 $cr15 $dr0 $dr1 $dr2 $dr3 $dr4 $dr5 $dr6 $dr7 $dr8 $dr9 $dr10 $dr11 $dr12 $dr13 $dr14 $dr15 $fp0 $fp1 $fp2 $fp3 $fp4 $fp5 $fp6 $fp7 $k0 $k1 $k2 $k3 $k4 $k5 $k6 $k7 $mm0 $mm1 $mm2 $mm3 $mm4 $mm5 $mm6 $mm7 $r11 $st0 $st1 $st2 $st3 $st4 $st5 $st6 $st7 $tmm0 $tmm1 $tmm2 $tmm3 $tmm4 $tmm5 $tmm6 $tmm7 $xmm16 $xmm17 $xmm18 $xmm19 $xmm20 $xmm21 $xmm22 $xmm23 $xmm24 $xmm25 $xmm26 $xmm27 $xmm28 $xmm29 $xmm30 $xmm31 $ymm0 $ymm1 $ymm2 $ymm3 $ymm4 $ymm5 $ymm6 $ymm7 $ymm8 $ymm9 $ymm10 $ymm11 $ymm12 $ymm13 $ymm14 $ymm15 $ymm16 $ymm17 $ymm18 $ymm19 $ymm20 $ymm21 $ymm22 $ymm23 $ymm24 $ymm25 $ymm26 $ymm27 $ymm28 $ymm29 $ymm30 $ymm31 $zmm0 $zmm1 $zmm2 $zmm3 $zmm4 $zmm5 $zmm6 $zmm7 $zmm8 $zmm9 $zmm10 $zmm11 $zmm12 $zmm13 $zmm14 $zmm15 $zmm16 $zmm17 $zmm18 $zmm19 $zmm20 $zmm21 $zmm22 $zmm23 $zmm24 $zmm25 $zmm26 $zmm27 $zmm28 $zmm29 $zmm30 $zmm31 $r11b $r11bh $r11d $r11w $r11wh $k0_k1 $k2_k3 $k4_k5 $k6_k7 +; CHECK: foo Clobbered Registers: $cs $df $ds $eflags $eip $eiz $es $esp $fpcw $fpsw $fs $gs $hip $hsp $ip $mxcsr $rip $riz $rsp $sp $sph $spl $ss $ssp $tmmcfg $cr0 $cr1 $cr2 $cr3 $cr4 $cr5 $cr6 $cr7 $cr8 $cr9 $cr10 $cr11 $cr12 $cr13 $cr14 $cr15 $dr0 $dr1 $dr2 $dr3 $dr4 $dr5 $dr6 $dr7 $dr8 $dr9 $dr10 $dr11 $dr12 $dr13 $dr14 $dr15 $fp0 $fp1 $fp2 $fp3 $fp4 $fp5 $fp6 $fp7 $k0 $k1 $k2 $k3 $k4 $k5 $k6 $k7 $mm0 $mm1 $mm2 $mm3 $mm4 $mm5 $mm6 $mm7 $r11 $st0 $st1 $st2 $st3 $st4 $st5 $st6 $st7 $tmm0 $tmm1 $tmm2 $tmm3 $tmm4 $tmm5 $tmm6 $tmm7 $xmm16 $xmm17 $xmm18 $xmm19 $xmm20 $xmm21 $xmm22 $xmm23 $xmm24 $xmm25 $xmm26 $xmm27 $xmm28 $xmm29 $xmm30 $xmm31 $ymm0 $ymm1 $ymm2 $ymm3 $ymm4 $ymm5 $ymm6 $ymm7 $ymm8 $ymm9 $ymm10 $ymm11 $ymm12 $ymm13 $ymm14 $ymm15 $ymm16 $ymm17 $ymm18 $ymm19 $ymm20 $ymm21 $ymm22 $ymm23 $ymm24 $ymm25 $ymm26 $ymm27 $ymm28 $ymm29 $ymm30 $ymm31 $zmm0 $zmm1 $zmm2 $zmm3 $zmm4 $zmm5 $zmm6 $zmm7 $zmm8 $zmm9 $zmm10 $zmm11 $zmm12 $zmm13 $zmm14 $zmm15 $zmm16 $zmm17 $zmm18 $zmm19 $zmm20 $zmm21 $zmm22 $zmm23 $zmm24 $zmm25 $zmm26 $zmm27 $zmm28 $zmm29 $zmm30 $zmm31 $r11b $r11bh $r11d $r11w $r11wh $k0_k1 $k2_k3 $k4_k5 $k6_k7 call void @bar1() call void @bar2() ret void diff --git a/llvm/test/MC/X86/mpx-encodings.s b/llvm/test/MC/X86/mpx-encodings.s deleted file mode 100644 index 3bdd08c..0000000 --- a/llvm/test/MC/X86/mpx-encodings.s +++ /dev/null @@ -1,41 +0,0 @@ -// RUN: llvm-mc -triple x86_64-- --show-encoding %s |\ -// RUN: FileCheck %s --check-prefixes=CHECK,ENCODING - -// RUN: llvm-mc -triple x86_64-- -filetype=obj %s |\ -// RUN: llvm-objdump -d - | FileCheck %s - -// CHECK: bndmk (%rax), %bnd0 -// ENCODING: encoding: [0xf3,0x0f,0x1b,0x00] -bndmk (%rax), %bnd0 - -// CHECK: bndmk 1024(%rax), %bnd1 -// ENCODING: encoding: [0xf3,0x0f,0x1b,0x88,0x00,0x04,0x00,0x00] -bndmk 1024(%rax), %bnd1 - -// CHECK: bndmov %bnd2, %bnd1 -// ENCODING: encoding: [0x66,0x0f,0x1a,0xca] -bndmov %bnd2, %bnd1 - -// CHECK: bndmov %bnd1, 1024(%r9) -// ENCODING: encoding: [0x66,0x41,0x0f,0x1b,0x89,0x00,0x04,0x00,0x00] -bndmov %bnd1, 1024(%r9) - -// CHECK: bndstx %bnd1, 1024(%rax) -// ENCODING: encoding: [0x0f,0x1b,0x88,0x00,0x04,0x00,0x00] -bndstx %bnd1, 1024(%rax) - -// CHECK: bndldx 1024(%r8), %bnd1 -// ENCODING: encoding: [0x41,0x0f,0x1a,0x88,0x00,0x04,0x00,0x00] -bndldx 1024(%r8), %bnd1 - -// CHECK: bndcl 121(%r10), %bnd1 -// ENCODING: encoding: [0xf3,0x41,0x0f,0x1a,0x4a,0x79] -bndcl 121(%r10), %bnd1 - -// CHECK: bndcn 121(%rcx), %bnd3 -// ENCODING: encoding: [0xf2,0x0f,0x1b,0x59,0x79] -bndcn 121(%rcx), %bnd3 - -// CHECK: bndcu %rdx, %bnd3 -// ENCODING: encoding: [0xf2,0x0f,0x1a,0xda] -bndcu %rdx, %bnd3 diff --git a/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp index b430caf..f4bf2d2 100644 --- a/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp @@ -213,26 +213,6 @@ TEST_F(X86SerialSnippetGeneratorTest, VCVTUSI642SDZrrb_Int) { ASSERT_TRUE(BC.Key.Instructions[0].getOperand(3).isImm()); } -TEST_F(X86ParallelSnippetGeneratorTest, ParallelInstruction) { - // - BNDCL32rr - // - Op0 Explicit Use RegClass(BNDR) - // - Op1 Explicit Use RegClass(GR32) - // - Var0 [Op0] - // - Var1 [Op1] - const unsigned Opcode = X86::BNDCL32rr; - const auto CodeTemplates = checkAndGetCodeTemplates(Opcode); - ASSERT_THAT(CodeTemplates, SizeIs(1)); - const auto &CT = CodeTemplates[0]; - EXPECT_THAT(CT.Info, HasSubstr("parallel")); - EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN); - ASSERT_THAT(CT.Instructions, SizeIs(1)); - const InstructionTemplate &IT = CT.Instructions[0]; - EXPECT_THAT(IT.getOpcode(), Opcode); - ASSERT_THAT(IT.getVariableValues(), SizeIs(2)); - EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()); - EXPECT_THAT(IT.getVariableValues()[1], IsInvalid()); -} - TEST_F(X86ParallelSnippetGeneratorTest, SerialInstruction) { // - CDQ // - Op0 Implicit Def Reg(EAX) -- 2.7.4