From c2b6c547dc28b5a50701a70f2295267ab9f05deb Mon Sep 17 00:00:00 2001 From: QingShan Zhang Date: Mon, 3 Sep 2018 03:14:29 +0000 Subject: [PATCH] [PowerPC] Add Itineraries of IIC_IntRotateDI for P7/P8 When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. Patch by jsji (Jinsong Ji) Differential Revision: https://reviews.llvm.org/D51506 llvm-svn: 341293 --- llvm/lib/Target/PowerPC/PPCScheduleP7.td | 4 ++ llvm/lib/Target/PowerPC/PPCScheduleP8.td | 4 ++ llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll | 16 +++---- llvm/test/CodeGen/PowerPC/funnel-shift.ll | 2 +- llvm/test/CodeGen/PowerPC/pr33093.ll | 58 ++++++++++++------------ llvm/test/CodeGen/PowerPC/testBitReverse.ll | 58 ++++++++++++------------ 6 files changed, 75 insertions(+), 67 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCScheduleP7.td b/llvm/lib/Target/PowerPC/PPCScheduleP7.td index a8678f5..a3634ff 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleP7.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleP7.td @@ -126,6 +126,10 @@ def P7Itineraries : ProcessorItineraries< P7_DU3, P7_DU4], 0>, InstrStage<1, [P7_FX1, P7_FX2]>], [1, 1, 1]>, + InstrItinData, + InstrStage<1, [P7_FX1, P7_FX2]>], + [1, 1, 1]>, InstrItinData, InstrStage<1, [P7_FX1, P7_FX2]>], diff --git a/llvm/lib/Target/PowerPC/PPCScheduleP8.td b/llvm/lib/Target/PowerPC/PPCScheduleP8.td index 79963dd..c7908ec 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleP8.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleP8.td @@ -102,6 +102,10 @@ def P8Itineraries : ProcessorItineraries< P8_DU4, P8_DU5, P8_DU6], 0>, InstrStage<1, [P8_FXU1, P8_FXU2]>], [1, 1, 1]>, + InstrItinData, + InstrStage<1, [P8_FXU1, P8_FXU2]>], + [1, 1, 1]>, InstrItinData, InstrStage<1, [P8_FXU1, P8_FXU2]>], diff --git a/llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll b/llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll index 479e33a..f249dd8 100644 --- a/llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll +++ b/llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll @@ -33,20 +33,20 @@ define signext i32 @main() { ; ; CHECK-P7-LABEL: main: ; CHECK-P7: li 3, -32477 -; CHECK-P7: lis 4, 0 +; CHECK-P7: lis 5, 0 ; CHECK-P7: li 7, 0 -; CHECK-P7: li 5, 234 ; CHECK-P7: sth 3, 46(1) -; CHECK-P7: ori 4, 4, 33059 -; CHECK-P7: rlwinm 3, 6, 3, 27, 27 +; CHECK-P7: li 6, 234 +; CHECK-P7: ori 5, 5, 33059 +; CHECK-P7: rlwinm 3, 4, 3, 27, 27 ; CHECK-P7: ori 7, 7, 65535 ; CHECK-P7: sync +; CHECK-P7: slw 6, 6, 3 ; CHECK-P7: slw 8, 5, 3 -; CHECK-P7: slw 9, 4, 3 -; CHECK-P7: rldicr 4, 6, 0, 61 ; CHECK-P7: slw 5, 7, 3 -; CHECK-P7: and 7, 8, 5 -; CHECK-P7: and 8, 9, 5 +; CHECK-P7: rldicr 4, 4, 0, 61 +; CHECK-P7: and 7, 6, 5 +; CHECK-P7: and 8, 8, 5 ; CHECK-P7: .LBB0_1: # %L.entry ; CHECK-P7: lwarx 9, 0, 4 ; CHECK-P7: and 6, 9, 5 diff --git a/llvm/test/CodeGen/PowerPC/funnel-shift.ll b/llvm/test/CodeGen/PowerPC/funnel-shift.ll index 05d105b..8a26f77 100644 --- a/llvm/test/CodeGen/PowerPC/funnel-shift.ll +++ b/llvm/test/CodeGen/PowerPC/funnel-shift.ll @@ -36,8 +36,8 @@ define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) { ; CHECK: # %bb.0: ; CHECK-NEXT: lis 6, -8857 ; CHECK-NEXT: clrldi 5, 5, 27 -; CHECK-NEXT: clrldi 4, 4, 27 ; CHECK-NEXT: ori 6, 6, 51366 +; CHECK-NEXT: clrldi 4, 4, 27 ; CHECK-NEXT: sldi 6, 6, 32 ; CHECK-NEXT: oris 6, 6, 3542 ; CHECK-NEXT: ori 6, 6, 31883 diff --git a/llvm/test/CodeGen/PowerPC/pr33093.ll b/llvm/test/CodeGen/PowerPC/pr33093.ll index 2b9291d..0853d2b 100644 --- a/llvm/test/CodeGen/PowerPC/pr33093.ll +++ b/llvm/test/CodeGen/PowerPC/pr33093.ll @@ -71,49 +71,49 @@ define i64 @ReverseBits64(i64 %n) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lis 4, -21846 ; CHECK-NEXT: lis 5, 21845 -; CHECK-NEXT: lis 6, -13108 -; CHECK-NEXT: lis 7, 13107 -; CHECK-NEXT: sldi 8, 3, 1 -; CHECK-NEXT: rldicl 3, 3, 63, 1 +; CHECK-NEXT: lis 7, -13108 +; CHECK-NEXT: lis 8, 13107 ; CHECK-NEXT: ori 4, 4, 43690 ; CHECK-NEXT: ori 5, 5, 21845 -; CHECK-NEXT: ori 6, 6, 52428 -; CHECK-NEXT: ori 7, 7, 13107 +; CHECK-NEXT: ori 7, 7, 52428 +; CHECK-NEXT: ori 8, 8, 13107 ; CHECK-NEXT: sldi 4, 4, 32 ; CHECK-NEXT: sldi 5, 5, 32 ; CHECK-NEXT: oris 4, 4, 43690 ; CHECK-NEXT: oris 5, 5, 21845 +; CHECK-NEXT: sldi 6, 3, 1 +; CHECK-NEXT: rldicl 3, 3, 63, 1 ; CHECK-NEXT: ori 4, 4, 43690 ; CHECK-NEXT: ori 5, 5, 21845 -; CHECK-NEXT: and 4, 8, 4 +; CHECK-NEXT: sldi 7, 7, 32 +; CHECK-NEXT: sldi 8, 8, 32 +; CHECK-NEXT: and 4, 6, 4 ; CHECK-NEXT: and 3, 3, 5 -; CHECK-NEXT: sldi 5, 6, 32 -; CHECK-NEXT: sldi 6, 7, 32 -; CHECK-NEXT: lis 7, 3855 +; CHECK-NEXT: lis 5, -3856 +; CHECK-NEXT: oris 6, 7, 52428 +; CHECK-NEXT: oris 7, 8, 13107 ; CHECK-NEXT: or 3, 3, 4 -; CHECK-NEXT: oris 4, 5, 52428 -; CHECK-NEXT: oris 5, 6, 13107 -; CHECK-NEXT: lis 6, -3856 -; CHECK-NEXT: ori 7, 7, 3855 +; CHECK-NEXT: lis 4, 3855 +; CHECK-NEXT: ori 5, 5, 61680 +; CHECK-NEXT: ori 6, 6, 52428 +; CHECK-NEXT: ori 7, 7, 13107 +; CHECK-NEXT: ori 4, 4, 3855 ; CHECK-NEXT: sldi 8, 3, 2 -; CHECK-NEXT: ori 4, 4, 52428 ; CHECK-NEXT: rldicl 3, 3, 62, 2 -; CHECK-NEXT: ori 5, 5, 13107 -; CHECK-NEXT: ori 6, 6, 61680 -; CHECK-NEXT: and 4, 8, 4 -; CHECK-NEXT: and 3, 3, 5 -; CHECK-NEXT: sldi 5, 6, 32 -; CHECK-NEXT: sldi 6, 7, 32 -; CHECK-NEXT: or 3, 3, 4 -; CHECK-NEXT: oris 4, 5, 61680 -; CHECK-NEXT: oris 5, 6, 3855 +; CHECK-NEXT: and 6, 8, 6 +; CHECK-NEXT: and 3, 3, 7 +; CHECK-NEXT: sldi 5, 5, 32 +; CHECK-NEXT: sldi 4, 4, 32 +; CHECK-NEXT: or 3, 3, 6 +; CHECK-NEXT: oris 5, 5, 61680 +; CHECK-NEXT: oris 4, 4, 3855 ; CHECK-NEXT: sldi 6, 3, 4 -; CHECK-NEXT: ori 4, 4, 61680 +; CHECK-NEXT: ori 5, 5, 61680 +; CHECK-NEXT: ori 4, 4, 3855 ; CHECK-NEXT: rldicl 3, 3, 60, 4 -; CHECK-NEXT: ori 5, 5, 3855 -; CHECK-NEXT: and 4, 6, 4 -; CHECK-NEXT: and 3, 3, 5 -; CHECK-NEXT: or 3, 3, 4 +; CHECK-NEXT: and 5, 6, 5 +; CHECK-NEXT: and 3, 3, 4 +; CHECK-NEXT: or 3, 3, 5 ; CHECK-NEXT: rldicl 4, 3, 32, 32 ; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31 ; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31 diff --git a/llvm/test/CodeGen/PowerPC/testBitReverse.ll b/llvm/test/CodeGen/PowerPC/testBitReverse.ll index 55a94d3..b6c78b4 100644 --- a/llvm/test/CodeGen/PowerPC/testBitReverse.ll +++ b/llvm/test/CodeGen/PowerPC/testBitReverse.ll @@ -47,49 +47,49 @@ define i64 @testBitReverseIntrinsicI64(i64 %arg) { ; CHECK: # %bb.0: ; CHECK-NEXT: lis 4, -21846 ; CHECK-NEXT: lis 5, 21845 -; CHECK-NEXT: lis 6, -13108 -; CHECK-NEXT: lis 7, 13107 -; CHECK-NEXT: sldi 8, 3, 1 -; CHECK-NEXT: rldicl 3, 3, 63, 1 +; CHECK-NEXT: lis 7, -13108 +; CHECK-NEXT: lis 8, 13107 ; CHECK-NEXT: ori 4, 4, 43690 ; CHECK-NEXT: ori 5, 5, 21845 -; CHECK-NEXT: ori 6, 6, 52428 -; CHECK-NEXT: ori 7, 7, 13107 +; CHECK-NEXT: ori 7, 7, 52428 +; CHECK-NEXT: ori 8, 8, 13107 ; CHECK-NEXT: sldi 4, 4, 32 ; CHECK-NEXT: sldi 5, 5, 32 ; CHECK-NEXT: oris 4, 4, 43690 ; CHECK-NEXT: oris 5, 5, 21845 +; CHECK-NEXT: sldi 6, 3, 1 +; CHECK-NEXT: rldicl 3, 3, 63, 1 ; CHECK-NEXT: ori 4, 4, 43690 ; CHECK-NEXT: ori 5, 5, 21845 -; CHECK-NEXT: and 4, 8, 4 +; CHECK-NEXT: sldi 7, 7, 32 +; CHECK-NEXT: sldi 8, 8, 32 +; CHECK-NEXT: and 4, 6, 4 ; CHECK-NEXT: and 3, 3, 5 -; CHECK-NEXT: sldi 5, 6, 32 -; CHECK-NEXT: sldi 6, 7, 32 -; CHECK-NEXT: lis 7, 3855 +; CHECK-NEXT: lis 5, -3856 +; CHECK-NEXT: oris 6, 7, 52428 +; CHECK-NEXT: oris 7, 8, 13107 ; CHECK-NEXT: or 3, 3, 4 -; CHECK-NEXT: oris 4, 5, 52428 -; CHECK-NEXT: oris 5, 6, 13107 -; CHECK-NEXT: lis 6, -3856 -; CHECK-NEXT: ori 7, 7, 3855 +; CHECK-NEXT: lis 4, 3855 +; CHECK-NEXT: ori 5, 5, 61680 +; CHECK-NEXT: ori 6, 6, 52428 +; CHECK-NEXT: ori 7, 7, 13107 +; CHECK-NEXT: ori 4, 4, 3855 ; CHECK-NEXT: sldi 8, 3, 2 -; CHECK-NEXT: ori 4, 4, 52428 ; CHECK-NEXT: rldicl 3, 3, 62, 2 -; CHECK-NEXT: ori 5, 5, 13107 -; CHECK-NEXT: ori 6, 6, 61680 -; CHECK-NEXT: and 4, 8, 4 -; CHECK-NEXT: and 3, 3, 5 -; CHECK-NEXT: sldi 5, 6, 32 -; CHECK-NEXT: sldi 6, 7, 32 -; CHECK-NEXT: or 3, 3, 4 -; CHECK-NEXT: oris 4, 5, 61680 -; CHECK-NEXT: oris 5, 6, 3855 +; CHECK-NEXT: and 6, 8, 6 +; CHECK-NEXT: and 3, 3, 7 +; CHECK-NEXT: sldi 5, 5, 32 +; CHECK-NEXT: sldi 4, 4, 32 +; CHECK-NEXT: or 3, 3, 6 +; CHECK-NEXT: oris 5, 5, 61680 +; CHECK-NEXT: oris 4, 4, 3855 ; CHECK-NEXT: sldi 6, 3, 4 -; CHECK-NEXT: ori 4, 4, 61680 +; CHECK-NEXT: ori 5, 5, 61680 +; CHECK-NEXT: ori 4, 4, 3855 ; CHECK-NEXT: rldicl 3, 3, 60, 4 -; CHECK-NEXT: ori 5, 5, 3855 -; CHECK-NEXT: and 4, 6, 4 -; CHECK-NEXT: and 3, 3, 5 -; CHECK-NEXT: or 3, 3, 4 +; CHECK-NEXT: and 5, 6, 5 +; CHECK-NEXT: and 3, 3, 4 +; CHECK-NEXT: or 3, 3, 5 ; CHECK-NEXT: rldicl 4, 3, 32, 32 ; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31 ; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31 -- 2.7.4