From c2741cbe7f8aba56a79a150536863eb1f62f9af6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 29 Sep 2022 16:54:16 +0200 Subject: [PATCH] dt-bindings: media: st,stmipid02: Convert the text bindings to YAML Convert the text STMIPID02 DT bindings to YAML DT format to permit validation of DTs using this I2C CSI-2 to CPI bridge. Reviewed-by: Benjamin Mugnier Signed-off-by: Marek Vasut Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20220929145416.16336-1-marex@denx.de Signed-off-by: Rob Herring --- .../bindings/media/i2c/st,st-mipid02.txt | 82 ---------- .../bindings/media/i2c/st,st-mipid02.yaml | 176 +++++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 177 insertions(+), 83 deletions(-) delete mode 100644 Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt create mode 100644 Documentation/devicetree/bindings/media/i2c/st,st-mipid02.yaml diff --git a/Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt b/Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt deleted file mode 100644 index 7976e6c..0000000 --- a/Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt +++ /dev/null @@ -1,82 +0,0 @@ -STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge - -MIPID02 has two CSI-2 input ports, only one of those ports can be active at a -time. Active port input stream will be de-serialized and its content outputted -through PARALLEL output port. -CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second -input port is a single lane 800Mbps. Both ports support clock and data lane -polarity swap. First port also supports data lane swap. -PARALLEL output port has a maximum width of 12 bits. -Supported formats are RAW6, RAW7, RAW8, RAW10, RAW12, RGB565, RGB888, RGB444, -YUV420 8-bit, YUV422 8-bit and YUV420 10-bit. - -Required Properties: -- compatible: shall be "st,st-mipid02" -- clocks: reference to the xclk input clock. -- clock-names: shall be "xclk". -- VDDE-supply: sensor digital IO supply. Must be 1.8 volts. -- VDDIN-supply: sensor internal regulator supply. Must be 1.8 volts. - -Optional Properties: -- reset-gpios: reference to the GPIO connected to the xsdn pin, if any. - This is an active low signal to the mipid02. - -Required subnodes: - - ports: A ports node with one port child node per device input and output - port, in accordance with the video interface bindings defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - port nodes are numbered as follows: - - Port Description - ----------------------------- - 0 CSI-2 first input port - 1 CSI-2 second input port - 2 PARALLEL output - -Endpoint node required property for CSI-2 connection is: -- data-lanes: shall be <1> for Port 1. for Port 0 dual-lane operation shall be -<1 2> or <2 1>. For Port 0 single-lane operation shall be <1> or <2>. -Endpoint node optional property for CSI-2 connection is: -- lane-polarities: any lane can be inverted or not. - -Endpoint node required property for PARALLEL connection is: -- bus-width: shall be set to <6>, <7>, <8>, <10> or <12>. -Endpoint node optional properties for PARALLEL connection are: -- hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively. -LOW being the default. -- vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively. -LOW being the default. - -Example: - -mipid02: csi2rx@14 { - compatible = "st,st-mipid02"; - reg = <0x14>; - status = "okay"; - clocks = <&clk_ext_camera_12>; - clock-names = "xclk"; - VDDE-supply = <&vdd>; - VDDIN-supply = <&vdd>; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - - ep0: endpoint { - data-lanes = <1 2>; - remote-endpoint = <&mipi_csi2_in>; - }; - }; - port@2 { - reg = <2>; - - ep2: endpoint { - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - remote-endpoint = <¶llel_out>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/i2c/st,st-mipid02.yaml b/Documentation/devicetree/bindings/media/i2c/st,st-mipid02.yaml new file mode 100644 index 0000000..19a39d7 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/st,st-mipid02.yaml @@ -0,0 +1,176 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/st,st-mipid02.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge + +maintainers: + - Benjamin Mugnier + - Sylvain Petinot + +description: + MIPID02 has two CSI-2 input ports, only one of those ports can be + active at a time. Active port input stream will be de-serialized + and its content outputted through PARALLEL output port. + CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 + second input port is a single lane 800Mbps. Both ports support clock + and data lane polarity swap. First port also supports data lane swap. + PARALLEL output port has a maximum width of 12 bits. + Supported formats are RAW6, RAW7, RAW8, RAW10, RAW12, RGB565, RGB888, + RGB444, YUV420 8-bit, YUV422 8-bit and YUV420 10-bit. + +properties: + compatible: + const: st,st-mipid02 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xclk + + VDDE-supply: + description: + Sensor digital IO supply. Must be 1.8 volts. + + VDDIN-supply: + description: + Sensor internal regulator supply. Must be 1.8 volts. + + reset-gpios: + description: + Reference to the GPIO connected to the xsdn pin, if any. + This is an active low signal to the mipid02. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI-2 first input port + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: + Single-lane operation shall be <1> or <2> . + Dual-lane operation shall be <1 2> or <2 1> . + minItems: 1 + maxItems: 2 + + lane-polarities: + description: + Any lane can be inverted or not. + minItems: 1 + maxItems: 2 + + required: + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI-2 second input port + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: + Single-lane operation shall be <1> or <2> . + maxItems: 1 + + lane-polarities: + description: + Any lane can be inverted or not. + maxItems: 1 + + required: + - data-lanes + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Output port + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + bus-width: + enum: [6, 7, 8, 10, 12] + + required: + - bus-width + + anyOf: + - required: + - port@0 + - required: + - port@1 + + required: + - port@2 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - VDDE-supply + - VDDIN-supply + - ports + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + mipid02: csi2rx@14 { + compatible = "st,st-mipid02"; + reg = <0x14>; + status = "okay"; + clocks = <&clk_ext_camera_12>; + clock-names = "xclk"; + VDDE-supply = <&vdd>; + VDDIN-supply = <&vdd>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + + ep0: endpoint { + data-lanes = <1 2>; + remote-endpoint = <&mipi_csi2_in>; + }; + }; + port@2 { + reg = <2>; + + ep2: endpoint { + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + remote-endpoint = <¶llel_out>; + }; + }; + }; + }; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index cf0f185..c379db6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19476,7 +19476,7 @@ M: Sylvain Petinot L: linux-media@vger.kernel.org S: Maintained T: git git://linuxtv.org/media_tree.git -F: Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt +F: Documentation/devicetree/bindings/media/i2c/st,st-mipid02.yaml F: drivers/media/i2c/st-mipid02.c ST STM32 I2C/SMBUS DRIVER -- 2.7.4