From c2493ce4a40be025054087fde59dd0f339baf6c0 Mon Sep 17 00:00:00 2001 From: Andrea Di Biagio Date: Sun, 26 May 2019 19:50:31 +0000 Subject: [PATCH] [MCA][Scheduler] Improved critical memory dependency computation. This fixes a problem where back-pressure increases caused by register dependencies were not correctly notified if execution was also delayed by memory dependencies. llvm-svn: 361740 --- llvm/lib/MCA/HardwareUnits/Scheduler.cpp | 22 ++++++++++++++++------ .../tools/llvm-mca/X86/BtVer2/bottleneck-hints-3.s | 2 +- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/llvm/lib/MCA/HardwareUnits/Scheduler.cpp b/llvm/lib/MCA/HardwareUnits/Scheduler.cpp index b2928ed..6b3448fb 100644 --- a/llvm/lib/MCA/HardwareUnits/Scheduler.cpp +++ b/llvm/lib/MCA/HardwareUnits/Scheduler.cpp @@ -105,7 +105,13 @@ void Scheduler::issueInstruction( // other dependent instructions. Dependent instructions may be issued during // this same cycle if operands have ReadAdvance entries. Promote those // instructions to the ReadySet and notify the caller that those are ready. - if (HasDependentUsers && promoteToPendingSet(PendingInstructions)) + // If IR is a memory operation, then always call method `promoteToReadySet()` + // to notify any dependent memory operations that IR started execution. + bool ShouldPromoteInstructions = Inst.isMemOp(); + if (HasDependentUsers) + ShouldPromoteInstructions |= promoteToPendingSet(PendingInstructions); + + if (ShouldPromoteInstructions) promoteToReadySet(ReadyInstructions); } @@ -287,15 +293,19 @@ uint64_t Scheduler::analyzeResourcePressure(SmallVectorImpl &Insts) { void Scheduler::analyzeDataDependencies(SmallVectorImpl &RegDeps, SmallVectorImpl &MemDeps) { const auto EndIt = PendingSet.end() - NumDispatchedToThePendingSet; - for (InstRef &IR : make_range(PendingSet.begin(), EndIt)) { - Instruction &IS = *IR.getInstruction(); + for (const InstRef &IR : make_range(PendingSet.begin(), EndIt)) { + const Instruction &IS = *IR.getInstruction(); if (Resources->checkAvailability(IS.getDesc())) continue; - if (IS.isReady() || (IS.isMemOp() && LSU.isReady(IR) != IR)) - MemDeps.emplace_back(IR); - else + const CriticalDependency &CMD = IS.getCriticalMemDep(); + if (IS.isMemOp() && IS.getCurrentMemDep() != &IS && !CMD.Cycles) + continue; + + if (IS.isPending()) RegDeps.emplace_back(IR); + if (CMD.Cycles) + MemDeps.emplace_back(IR); } } diff --git a/llvm/test/tools/llvm-mca/X86/BtVer2/bottleneck-hints-3.s b/llvm/test/tools/llvm-mca/X86/BtVer2/bottleneck-hints-3.s index 6cd613a..bedfef1 100644 --- a/llvm/test/tools/llvm-mca/X86/BtVer2/bottleneck-hints-3.s +++ b/llvm/test/tools/llvm-mca/X86/BtVer2/bottleneck-hints-3.s @@ -24,7 +24,7 @@ vmovaps %xmm0, 48(%rdi) # CHECK-NEXT: Throughput Bottlenecks: # CHECK-NEXT: Resource Pressure [ 0.00% ] # CHECK-NEXT: Data Dependencies: [ 99.89% ] -# CHECK-NEXT: - Register Dependencies [ 0.00% ] +# CHECK-NEXT: - Register Dependencies [ 83.24% ] # CHECK-NEXT: - Memory Dependencies [ 99.89% ] # CHECK: Instruction Info: -- 2.7.4