From c1cef111a3bf02c602125c9a6e5c1f18ad857a62 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sat, 5 Feb 2022 12:51:01 -0800 Subject: [PATCH] Revert "[RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X)." This reverts commit 673d68cd923a9daa5065b929453bf4a4b8d39650. This hadn't been reviewed yet. --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 17 ----------------- llvm/lib/Target/RISCV/RISCVISelLowering.h | 2 -- llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td | 7 ++----- llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll | 2 ++ 4 files changed, 4 insertions(+), 24 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index ce3bd8dd2f58..c6abad23b5ae 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -1069,8 +1069,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setTargetDAGCombine(ISD::OR); setTargetDAGCombine(ISD::XOR); setTargetDAGCombine(ISD::ANY_EXTEND); - if (Subtarget.hasStdExtZfh()) - setTargetDAGCombine(ISD::SIGN_EXTEND_INREG); if (Subtarget.hasStdExtF()) { setTargetDAGCombine(ISD::ZERO_EXTEND); setTargetDAGCombine(ISD::FP_TO_SINT); @@ -7357,18 +7355,6 @@ static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG) { return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false); } -static SDValue performSIGN_EXTEND_INREG(SDNode *N, SelectionDAG &DAG) { - SDValue Src = N->getOperand(0); - - // Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X) - if (Src.getOpcode() == RISCVISD::FMV_X_ANYEXTH && - cast(N->getOperand(1))->getVT().bitsGE(MVT::i16)) - return DAG.getNode(RISCVISD::FMV_X_SIGNEXTH, SDLoc(N), N->getValueType(0), - Src.getOperand(0)); - - return SDValue(); -} - // Attempt to turn ANY_EXTEND into SIGN_EXTEND if the input to the ANY_EXTEND // has users that require SIGN_EXTEND and the SIGN_EXTEND can be done for free // by an instruction like ADDW/SUBW/MULW. Without this the ANY_EXTEND would be @@ -7955,8 +7941,6 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, return performORCombine(N, DAG, Subtarget); case ISD::XOR: return performXORCombine(N, DAG); - case ISD::SIGN_EXTEND_INREG: - return performSIGN_EXTEND_INREG(N, DAG); case ISD::ANY_EXTEND: return performANY_EXTENDCombine(N, DCI, Subtarget); case ISD::ZERO_EXTEND: @@ -10352,7 +10336,6 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const { NODE_NAME_CASE(FSR) NODE_NAME_CASE(FMV_H_X) NODE_NAME_CASE(FMV_X_ANYEXTH) - NODE_NAME_CASE(FMV_X_SIGNEXTH) NODE_NAME_CASE(FMV_W_X_RV64) NODE_NAME_CASE(FMV_X_ANYEXTW_RV64) NODE_NAME_CASE(FCVT_X) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index f840ea18a205..2d1da98588d5 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -75,7 +75,6 @@ enum NodeType : unsigned { // // FMV_H_X matches the semantics of the FMV.H.X. // FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result. - // FMV_X_SIGNEXTH is similar to FMV.X.H and has a sign-extended result. // FMV_W_X_RV64 matches the semantics of the FMV.W.X. // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result. // @@ -83,7 +82,6 @@ enum NodeType : unsigned { // unnecessary GPR->FPR->GPR moves. FMV_H_X, FMV_X_ANYEXTH, - FMV_X_SIGNEXTH, FMV_W_X_RV64, FMV_X_ANYEXTW_RV64, // FP to XLen int conversions. Corresponds to fcvt.l(u).s/d/h on RV64 and diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td index 6f6afb69c5d3..a2753c132354 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td @@ -17,15 +17,13 @@ def SDT_RISCVFMV_H_X : SDTypeProfile<1, 1, [SDTCisVT<0, f16>, SDTCisVT<1, XLenVT>]>; -def SDT_RISCVFMV_X_EXTH +def SDT_RISCVFMV_X_ANYEXTH : SDTypeProfile<1, 1, [SDTCisVT<0, XLenVT>, SDTCisVT<1, f16>]>; def riscv_fmv_h_x : SDNode<"RISCVISD::FMV_H_X", SDT_RISCVFMV_H_X>; def riscv_fmv_x_anyexth - : SDNode<"RISCVISD::FMV_X_ANYEXTH", SDT_RISCVFMV_X_EXTH>; -def riscv_fmv_x_signexth - : SDNode<"RISCVISD::FMV_X_SIGNEXTH", SDT_RISCVFMV_X_EXTH>; + : SDNode<"RISCVISD::FMV_X_ANYEXTH", SDT_RISCVFMV_X_ANYEXTH>; //===----------------------------------------------------------------------===// // Instructions @@ -301,7 +299,6 @@ def : Pat<(any_fpextend FPR16:$rs1), (FCVT_S_H FPR16:$rs1)>; // Moves (no conversion) def : Pat<(riscv_fmv_h_x GPR:$src), (FMV_H_X GPR:$src)>; def : Pat<(riscv_fmv_x_anyexth FPR16:$src), (FMV_X_H FPR16:$src)>; -def : Pat<(riscv_fmv_x_signexth FPR16:$src), (FMV_X_H FPR16:$src)>; } // Predicates = [HasStdExtZfhOrZfhmin] let Predicates = [HasStdExtZfh, IsRV32] in { diff --git a/llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll b/llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll index 3f5de3430993..f6844b48c71b 100644 --- a/llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll +++ b/llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll @@ -79,6 +79,8 @@ define signext i16 @bcvt_f16_to_sext_i16(half %a, half %b) nounwind { ; RV64IZFH: # %bb.0: ; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1 ; RV64IZFH-NEXT: fmv.x.h a0, ft0 +; RV64IZFH-NEXT: slli a0, a0, 48 +; RV64IZFH-NEXT: srai a0, a0, 48 ; RV64IZFH-NEXT: ret %1 = fadd half %a, %b %2 = bitcast half %1 to i16 -- 2.34.1