From c1756e6dc725b8a77ff98fa22f302af9f0244c00 Mon Sep 17 00:00:00 2001 From: "m.hayes" Date: Fri, 15 Oct 1999 05:39:23 +0000 Subject: [PATCH] * config/c4x/c4x.md: Define mode for remaining unspec operators. * config/c4x/c4x.c (dst_operand): Use nonimmediate_operand. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@30000 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 5 +++++ gcc/config/c4x/c4x.c | 7 ++++--- gcc/config/c4x/c4x.md | 28 ++++++++++++++-------------- 3 files changed, 23 insertions(+), 17 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5dacdbd..1052217 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +Fri Oct 15 18:36:07 1999 Michael Hayes + + * config/c4x/c4x.md: Define mode for remaining unspec operators. + * config/c4x/c4x.c (dst_operand): Use nonimmediate_operand. + Thu Oct 14 22:14:23 1999 Richard Henderson * i386.md (movstricthi_1): Allow r/r. diff --git a/gcc/config/c4x/c4x.c b/gcc/config/c4x/c4x.c index a731fbd..837d03d 100644 --- a/gcc/config/c4x/c4x.c +++ b/gcc/config/c4x/c4x.c @@ -593,6 +593,7 @@ c4x_function_arg (cum, mode, type, named) return NULL_RTX; } + void c4x_va_start (stdarg_p, valist, nextarg) int stdarg_p; @@ -604,9 +605,9 @@ c4x_va_start (stdarg_p, valist, nextarg) std_expand_builtin_va_start (stdarg_p, valist, nextarg); } + /* C[34]x arguments grow in weird ways (downwards) that the standard varargs stuff can't handle. */ - rtx c4x_va_arg (valist, type) tree valist, type; @@ -620,6 +621,7 @@ c4x_va_arg (valist, type) return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL); } + static int c4x_isr_reg_used_p (regno) int regno; @@ -3059,7 +3061,6 @@ symbolic_address_operand (op, mode) } } - /* Check dst operand of a move instruction. */ int dst_operand (op, mode) @@ -3073,7 +3074,7 @@ dst_operand (op, mode) if (REG_P (op)) return reg_operand (op, mode); - return memory_operand (op, mode); + return nonimmediate_operand (op, mode); } diff --git a/gcc/config/c4x/c4x.md b/gcc/config/c4x/c4x.md index a2bb7c21..d8979b6 100644 --- a/gcc/config/c4x/c4x.md +++ b/gcc/config/c4x/c4x.md @@ -2639,7 +2639,7 @@ (define_insn "*lshlqi3_clobber" [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c") (ashift:QI (match_operand:QI 1 "src_operand" "0,rR,rS<>,0,rR,rS<>") - (unspec [(match_operand:QI 2 "src_operand" "rIm,JR,rS<>,rIm,JR,rS<>")] 3))) + (unspec:QI [(match_operand:QI 2 "src_operand" "rIm,JR,rS<>,rIm,JR,rS<>")] 3))) (clobber (reg:CC 21))] "valid_operands (ASHIFT, operands, QImode)" "@ @@ -3587,7 +3587,7 @@ ; Inlined float square root for C4x (define_expand "sqrtqf2_inline" [(parallel [(set (match_dup 2) - (unspec [(match_operand:QF 1 "src_operand" "")] 10)) + (unspec:QF [(match_operand:QF 1 "src_operand" "")] 10)) (clobber (reg:CC_NOOV 21))]) (parallel [(set (match_dup 3) (mult:QF (match_dup 5) (match_dup 1))) (clobber (reg:CC_NOOV 21))]) @@ -3610,7 +3610,7 @@ (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 1))) (clobber (reg:CC_NOOV 21))]) (parallel [(set (match_operand:QF 0 "reg_operand" "") - (unspec [(match_dup 4)] 6)) + (unspec:QF [(match_dup 4)] 6)) (clobber (reg:CC_NOOV 21))])] "! TARGET_C3X" "if (! reload_in_progress @@ -3836,7 +3836,7 @@ ; Inlined float divide for C4x (define_expand "divqf3_inline" [(parallel [(set (match_dup 3) - (unspec [(match_operand:QF 2 "src_operand" "")] 5)) + (unspec:QF [(match_operand:QF 2 "src_operand" "")] 5)) (clobber (reg:CC_NOOV 21))]) (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 3))) (clobber (reg:CC_NOOV 21))]) @@ -3855,7 +3855,7 @@ (match_dup 3))) (clobber (reg:CC_NOOV 21))]) (parallel [(set (match_operand:QF 0 "reg_operand" "") - (unspec [(match_dup 3)] 6)) + (unspec:QF [(match_dup 3)] 6)) (clobber (reg:CC_NOOV 21))])] "! TARGET_C3X" "if (! reload_in_progress @@ -5267,7 +5267,7 @@ (match_operand:HF 1 "reg_operand" ""))] "reload_completed" [(set (match_dup 2) (float_truncate:QF (match_dup 1))) - (set (match_dup 3) (unspec [(match_dup 1)] 9))] + (set (match_dup 3) (unspec:QI [(match_dup 1)] 9))] "operands[2] = c4x_operand_subword (operands[0], 0, 1, HFmode); operands[3] = c4x_operand_subword (operands[0], 1, 1, HFmode); PUT_MODE (operands[2], QFmode); @@ -5337,7 +5337,7 @@ [(set (mem:QF (pre_inc:QI (reg:QI 20))) (float_truncate:QF (match_dup 0))) (set (mem:QI (pre_inc:QI (reg:QI 20))) - (unspec [(match_dup 0)] 9))] + (unspec:QI [(match_dup 0)] 9))] "") (define_insn "pushhf_trunc" @@ -5519,7 +5519,7 @@ ; Inlined float square root for C4x (define_expand "sqrthf2_inline" [(parallel [(set (match_dup 2) - (unspec [(match_operand:HF 1 "reg_operand" "")] 10)) + (unspec:HF [(match_operand:HF 1 "reg_operand" "")] 10)) (clobber (reg:CC_NOOV 21))]) (parallel [(set (match_dup 3) (mult:HF (match_dup 5) (match_dup 1))) (clobber (reg:CC_NOOV 21))]) @@ -5676,7 +5676,7 @@ ; Inlined float divide for C4x (define_expand "divhf3_inline" [(parallel [(set (match_dup 3) - (unspec [(match_operand:HF 2 "reg_operand" "")] 5)) + (unspec:HF [(match_operand:HF 2 "reg_operand" "")] 5)) (clobber (reg:CC_NOOV 21))]) (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 3))) (clobber (reg:CC_NOOV 21))]) @@ -6261,7 +6261,7 @@ /* If the shift count is greater than 32 this will do an arithmetic right shift. However, we need a logical right shift. */ (parallel [(set (match_dup 9) - (ashift:QI (match_dup 4) (unspec [(match_dup 10)] 3))) + (ashift:QI (match_dup 4) (unspec:QI [(match_dup 10)] 3))) (clobber (reg:CC 21))]) (set (match_dup 6) (match_dup 8)) (parallel [(set (match_dup 5) @@ -6368,8 +6368,8 @@ (match_operand:HI 1 "src_operand" "")))] "! reload_completed" [(parallel [(set (reg:CC 21) - (unspec [(compare:CC (match_dup 0) - (match_dup 1))] 4)) + (unspec:CC [(compare:CC (match_dup 0) + (match_dup 1))] 4)) (clobber (match_scratch:QI 2 "")) (clobber (match_scratch:QI 3 ""))])] "") @@ -6380,8 +6380,8 @@ (match_operand:HI 1 "src_operand" "")))] "! reload_completed" [(parallel [(set (reg:CC_NOOV 21) - (unspec [(compare:CC_NOOV (match_dup 0) - (match_dup 1))] 4)) + (unspec:CC_NOOV [(compare:CC_NOOV (match_dup 0) + (match_dup 1))] 4)) (clobber (match_scratch:QI 2 "")) (clobber (match_scratch:QI 3 ""))])] "") -- 2.7.4