From c15d7f893c0549282268de063d1bf1c57b3f080b Mon Sep 17 00:00:00 2001 From: "Mark F. Brown" Date: Thu, 23 Feb 2012 18:07:06 -0800 Subject: [PATCH] merrifield: initial platform code BZ: 25129 INTEL_MID_CPU_CHIP_TANGIER support added mrfl soc platform specific code added board-vp virtual platform specific code added apb timers are deprecated in tangier Change-Id: I5d5230e6ba78662e9d43bd11ba2d062ebc782255 Signed-off-by: Mark F. Brown Reviewed-on: http://android.intel.com:8080/36583 Reviewed-by: Ng, Cheon-woei Tested-by: Ng, Cheon-woei Reviewed-by: buildbot Tested-by: buildbot --- arch/x86/Kconfig | 19 +++++++++++++ arch/x86/include/asm/apb_timer.h | 1 + arch/x86/include/asm/intel-mid.h | 20 ++++++++++++++ arch/x86/platform/intel-mid/Makefile | 3 +++ arch/x86/platform/intel-mid/board-vp.c | 17 ++++++++++++ arch/x86/platform/intel-mid/intel-mid.c | 14 ++++++++++ arch/x86/platform/intel-mid/mrfl.c | 47 +++++++++++++++++++++++++++++++++ 7 files changed, 121 insertions(+) create mode 100644 arch/x86/platform/intel-mid/board-vp.c create mode 100644 arch/x86/platform/intel-mid/mrfl.c diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index a2b1d04..6932912 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -435,6 +435,19 @@ config X86_MDFLD nor standard legacy replacement devices/features. e.g. Medfield does not contain i8259, i8254, HPET, legacy BIOS, most of the io ports. +config X86_MRFLD + bool "Merrifield MID platform" + depends on PCI + depends on PCI_GOANY + depends on X86_IO_APIC + select INTEL_SCU_IPC + select X86_PLATFORM_DEVICES + ---help--- + Merrifield is Intel's Low Power Intel Architecture (LPIA) based Moblin + Internet Device(MID) platform. + Unlike Medfield, Merrifield does have many legacy devices supported + by the iLB unit. That includes i8259, i8254, HPET, ACPI, and RTC. + choice prompt "Intel MID board type" depends on X86_INTEL_MID @@ -475,6 +488,12 @@ config BOARD_CTP shares all the codes with Medfield except the board file(i.e. only platform devices and platform device data are different) +config BOARD_MRFLD_VP + bool "Merrifield simulation platform board type" + depends on X86_MRFLD + ---help--- + Merrifield based simulation configuration. This includes: + VP, HVP, SLE targets. endchoice endif diff --git a/arch/x86/include/asm/apb_timer.h b/arch/x86/include/asm/apb_timer.h index af60d8a..4586388 100644 --- a/arch/x86/include/asm/apb_timer.h +++ b/arch/x86/include/asm/apb_timer.h @@ -63,6 +63,7 @@ extern int sfi_mtimer_num; static inline unsigned long apbt_quick_calibrate(void) {return 0; } static inline void apbt_time_init(void) { } +static inline apbt_setup_secondary_clock(void) { } #endif #endif /* ASM_X86_APBT_H */ diff --git a/arch/x86/include/asm/intel-mid.h b/arch/x86/include/asm/intel-mid.h index 5a9ee14..783b45c 100644 --- a/arch/x86/include/asm/intel-mid.h +++ b/arch/x86/include/asm/intel-mid.h @@ -76,6 +76,7 @@ enum intel_mid_cpu_type { INTEL_MID_CPU_CHIP_LINCROFT = 1, INTEL_MID_CPU_CHIP_PENWELL, INTEL_MID_CPU_CHIP_CLOVERVIEW, + INTEL_MID_CPU_CHIP_TANGIER, }; extern enum intel_mid_cpu_type __intel_mid_cpu_chip; @@ -200,4 +201,23 @@ extern int get_force_shutdown_occured(void); extern const struct atomisp_platform_data *intel_get_v4l2_subdev_table(void); extern void (*saved_shutdown)(void); + +#ifdef CONFIG_X86_MRFLD +enum intel_mrfl_sim_type { + INTEL_MRFL_CPU_SIMULATION_NONE = 0, + INTEL_MRFL_CPU_SIMULATION_VP, + INTEL_MRFL_CPU_SIMULATION_SLE, +}; + +extern enum intel_mrfl_sim_type __intel_mrfl_sim_platform; + +static inline enum intel_mrfl_sim_type intel_mrfl_identify_sim(void) +{ + return __intel_mrfl_sim_platform; +} + +#else /* !CONFIG_X86_MRFLD */ +#define intel_mrfl_identify_sim() (0) +#endif /* !CONFIG_X86_MRFLD */ + #endif /* _ASM_X86_INTEL_MID_H */ diff --git a/arch/x86/platform/intel-mid/Makefile b/arch/x86/platform/intel-mid/Makefile index 9daec60..ed10386 100644 --- a/arch/x86/platform/intel-mid/Makefile +++ b/arch/x86/platform/intel-mid/Makefile @@ -10,7 +10,10 @@ obj-$(CONFIG_X86_MRST) += mrst-pmu.o # MFLD specific files obj-$(CONFIG_X86_MDFLD) += mfld.o obj-$(CONFIG_INTEL_MID_MDFLD_POWER) += mfld-pmu.o +# MRFL specific file +obj-$(CONFIG_X86_MRFLD) += mrfl.o # BOARD files obj-$(CONFIG_BOARD_MFLD_BLACKBAY) += board-blackbay.o obj-$(CONFIG_BOARD_REDRIDGE) += board-redridge.o obj-$(CONFIG_BOARD_CTP) += board-ctp.o +obj-$(CONFIG_BOARD_MRFLD_VP) += board-vp.o diff --git a/arch/x86/platform/intel-mid/board-vp.c b/arch/x86/platform/intel-mid/board-vp.c new file mode 100644 index 0000000..a2e90f0 --- /dev/null +++ b/arch/x86/platform/intel-mid/board-vp.c @@ -0,0 +1,17 @@ +/* + * board-vp.c: Intel Merrifield based board (Virtual Platform) + * + * (C) Copyright 2012 Intel Corporation + * Author: Mark F. Brown + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; version 2 + * of the License. + */ + +/* not supported */ +int penwell_otg_query_charging_cap(void *dummy) +{ + return -1; +} diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c index 078dff6..dbd82fc 100644 --- a/arch/x86/platform/intel-mid/intel-mid.c +++ b/arch/x86/platform/intel-mid/intel-mid.c @@ -79,6 +79,11 @@ static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM]; enum intel_mid_cpu_type __intel_mid_cpu_chip; EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip); +#ifdef CONFIG_X86_MRFLD +enum intel_mrfl_sim_type __intel_mrfl_sim_platform; +EXPORT_SYMBOL_GPL(__intel_mrfl_sim_platform); +#endif /* X86_CONFIG_MRFLD */ + int sfi_mtimer_num; struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX]; @@ -214,6 +219,13 @@ unsigned long __init intel_mid_calibrate_tsc(void) static void __init intel_mid_time_init(void) { sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr); + +/* [REVERT ME] ARAT capability not set in VP. Force setting */ +#ifdef CONFIG_X86_MRFLD + if (intel_mrfl_identify_sim() == INTEL_MRFL_CPU_SIMULATION_VP) + set_cpu_cap(&boot_cpu_data, X86_FEATURE_ARAT); +#endif /* CONFIG_X86_MRFLD */ + switch (intel_mid_timer_options) { case INTEL_MID_TIMER_APBT_ONLY: break; @@ -241,6 +253,8 @@ static void __cpuinit intel_mid_arch_setup(void) __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_LINCROFT; else if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x35) __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_CLOVERVIEW; + else if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x3C) + __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_TANGIER; else { pr_err("Unknown Moorestown CPU (%d:%d), default to Lincroft\n", boot_cpu_data.x86, boot_cpu_data.x86_model); diff --git a/arch/x86/platform/intel-mid/mrfl.c b/arch/x86/platform/intel-mid/mrfl.c new file mode 100644 index 0000000..082bca1 --- /dev/null +++ b/arch/x86/platform/intel-mid/mrfl.c @@ -0,0 +1,47 @@ +/* + * mrfl.c: Intel Merrifield platform specific setup code + * + * (C) Copyright 2012 Intel Corporation + * Author: Mark F. Brown + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; version 2 + * of the License. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +unsigned long __init intel_mid_calibrate_tsc(void) +{ + /* [REVERT ME] fast timer calibration method to be defined */ + if (intel_mrfl_identify_sim() == INTEL_MRFL_CPU_SIMULATION_VP) { + lapic_timer_frequency = 50000; + return 1000000; + } + + return 0; +} + +/* Allow user to enable simulator quirks settings for kernel */ +static int __init set_simulation_platform(char *str) +{ + int platform; + if (get_option(&str, &platform)) { + __intel_mrfl_sim_platform = platform; + pr_info("simulator mode %d enabled.\n", + __intel_mrfl_sim_platform); + return 0; + } + + return -EINVAL; +} +early_param("mrfld_simulation", set_simulation_platform); -- 2.7.4