From c13616906231cbabe68779adcf0f11c97197dd6b Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 17 Aug 2023 12:05:18 +0200 Subject: [PATCH] radv: fix emitting TCS epilogs for GFX6-9 The number of SGPRs need to be adjusted. Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index f0b2ac3..1634c2d 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1821,17 +1821,20 @@ radv_emit_ps_epilog_state(struct radv_cmd_buffer *cmd_buffer, struct radv_shader static void radv_emit_tcs_epilog_state(struct radv_cmd_buffer *cmd_buffer, struct radv_shader_part *tcs_epilog) { + const enum amd_gfx_level gfx_level = cmd_buffer->device->physical_device->rad_info.gfx_level; struct radv_shader *tcs_shader = cmd_buffer->state.shaders[MESA_SHADER_TESS_CTRL]; if (cmd_buffer->state.emitted_tcs_epilog == tcs_epilog) return; assert(tcs_shader->config.num_shared_vgprs == 0); - if (G_00B848_VGPRS(tcs_epilog->rsrc1) > G_00B848_VGPRS(tcs_shader->config.rsrc1)) { - uint32_t rsrc1 = tcs_shader->config.rsrc1; + uint32_t rsrc1 = tcs_shader->config.rsrc1; + if (G_00B848_VGPRS(tcs_epilog->rsrc1) > G_00B848_VGPRS(tcs_shader->config.rsrc1)) rsrc1 = (rsrc1 & C_00B848_VGPRS) | (tcs_epilog->rsrc1 & ~C_00B848_VGPRS); + if (gfx_level < GFX10 && G_00B228_SGPRS(tcs_epilog->rsrc1) > G_00B228_SGPRS(tcs_shader->config.rsrc1)) + rsrc1 = (rsrc1 & C_00B228_SGPRS) | (tcs_epilog->rsrc1 & ~C_00B228_SGPRS); + if (rsrc1 != tcs_shader->config.rsrc1) radeon_set_sh_reg(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, rsrc1); - } radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, tcs_epilog->bo); -- 2.7.4