From c0f1929dd23bbc558e9eef0f8fd40e10dfef3c21 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 19 May 2014 10:10:01 -0700 Subject: [PATCH] i965: Move dispatch_grf_start_reg and first_curbe_grf into stage_prog_data. I wanted to access this value from stage-generic code, so stop storing it under two different names. Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_context.h | 15 +++++++-------- src/mesa/drivers/dri/i965/brw_fs.cpp | 4 ++-- src/mesa/drivers/dri/i965/brw_vec4.cpp | 4 ++-- src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 2 +- src/mesa/drivers/dri/i965/brw_vs_state.c | 2 +- src/mesa/drivers/dri/i965/brw_wm_state.c | 7 ++++--- src/mesa/drivers/dri/i965/gen6_vs_state.c | 2 +- src/mesa/drivers/dri/i965/gen6_wm_state.c | 11 ++++++----- src/mesa/drivers/dri/i965/gen7_gs_state.c | 2 +- src/mesa/drivers/dri/i965/gen7_vs_state.c | 2 +- src/mesa/drivers/dri/i965/gen7_wm_state.c | 8 ++++---- src/mesa/drivers/dri/i965/gen8_gs_state.c | 2 +- src/mesa/drivers/dri/i965/gen8_ps_state.c | 8 ++++---- src/mesa/drivers/dri/i965/gen8_vs_state.c | 2 +- 14 files changed, 36 insertions(+), 35 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index c0cb267..7aa9484 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -297,6 +297,12 @@ struct brw_stage_prog_data { GLuint nr_params; /**< number of float params/constants */ GLuint nr_pull_params; + /** + * Register where the thread expects to find input data from the URB + * (typically uniforms, followed by vertex or fragment attributes). + */ + unsigned dispatch_grf_start_reg; + /* Pointers to tracked values (only valid once * _mesa_load_state_parameters has been called at runtime). * @@ -321,8 +327,7 @@ struct brw_wm_prog_data { GLuint curb_read_length; GLuint num_varying_inputs; - GLuint first_curbe_grf; - GLuint first_curbe_grf_16; + GLuint dispatch_grf_start_reg_16; GLuint reg_blocks; GLuint reg_blocks_16; GLuint total_scratch; @@ -524,12 +529,6 @@ struct brw_vec4_prog_data { struct brw_stage_prog_data base; struct brw_vue_map vue_map; - /** - * Register where the thread expects to find input data from the URB - * (typically uniforms, followed by per-vertex inputs). - */ - unsigned dispatch_grf_start_reg; - GLuint curb_read_length; GLuint urb_read_length; GLuint total_grf; diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index d22b1bf..8f20b68 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -1465,9 +1465,9 @@ void fs_visitor::assign_curb_setup() { if (dispatch_width == 8) { - prog_data->first_curbe_grf = payload.num_regs; + prog_data->base.dispatch_grf_start_reg = payload.num_regs; } else { - prog_data->first_curbe_grf_16 = payload.num_regs; + prog_data->dispatch_grf_start_reg_16 = payload.num_regs; } prog_data->curb_read_length = ALIGN(stage_prog_data->nr_params, 8) / 8; diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index 6927297..d9cde25 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp @@ -1529,7 +1529,7 @@ vec4_vs_visitor::setup_attributes(int payload_reg) int vec4_visitor::setup_uniforms(int reg) { - prog_data->dispatch_grf_start_reg = reg; + prog_data->base.dispatch_grf_start_reg = reg; /* The pre-gen6 VS requires that some push constants get loaded no * matter what, or the GPU would hang. @@ -1554,7 +1554,7 @@ vec4_visitor::setup_uniforms(int reg) stage_prog_data->nr_params = this->uniforms * 4; - prog_data->curb_read_length = reg - prog_data->dispatch_grf_start_reg; + prog_data->curb_read_length = reg - prog_data->base.dispatch_grf_start_reg; return reg; } diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp index bc6d1e5..07e29a5 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp @@ -98,7 +98,7 @@ vec4_instruction::get_src(const struct brw_vec4_prog_data *prog_data, int i) break; case UNIFORM: - brw_reg = stride(brw_vec4_grf(prog_data->dispatch_grf_start_reg + + brw_reg = stride(brw_vec4_grf(prog_data->base.dispatch_grf_start_reg + (src[i].reg + src[i].reg_offset) / 2, ((src[i].reg + src[i].reg_offset) % 2) * 4), 0, 4, 1); diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c index 7d5f511..a0710ab 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_state.c +++ b/src/mesa/drivers/dri/i965/brw_vs_state.c @@ -96,7 +96,7 @@ brw_upload_vs_unit(struct brw_context *brw) vs->thread3.const_urb_entry_read_length = brw->vs.prog_data->base.curb_read_length; vs->thread3.dispatch_grf_start_reg = - brw->vs.prog_data->base.dispatch_grf_start_reg; + brw->vs.prog_data->base.base.dispatch_grf_start_reg; vs->thread3.urb_entry_read_offset = 0; /* BRW_NEW_CURBE_OFFSETS, _NEW_TRANSFORM, BRW_NEW_VERTEX_PROGRAM */ diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c index 98b5185..84d39c1 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_state.c @@ -87,8 +87,8 @@ brw_upload_wm_unit(struct brw_context *brw) * only have one hardware field to program for both dispatch * widths. */ - assert(brw->wm.prog_data->first_curbe_grf == - brw->wm.prog_data->first_curbe_grf_16); + assert(brw->wm.prog_data->base.dispatch_grf_start_reg == + brw->wm.prog_data->dispatch_grf_start_reg_16); } /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_WM_PROG */ @@ -134,7 +134,8 @@ brw_upload_wm_unit(struct brw_context *brw) wm->thread2.per_thread_scratch_space = 0; } - wm->thread3.dispatch_grf_start_reg = brw->wm.prog_data->first_curbe_grf; + wm->thread3.dispatch_grf_start_reg = + brw->wm.prog_data->base.dispatch_grf_start_reg; wm->thread3.urb_entry_read_length = brw->wm.prog_data->num_varying_inputs * 2; wm->thread3.urb_entry_read_offset = 0; diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c index 62fbd6c..9d3c184 100644 --- a/src/mesa/drivers/dri/i965/gen6_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c @@ -186,7 +186,7 @@ upload_vs_state(struct brw_context *brw) OUT_BATCH(0); } - OUT_BATCH((brw->vs.prog_data->base.dispatch_grf_start_reg << + OUT_BATCH((brw->vs.prog_data->base.base.dispatch_grf_start_reg << GEN6_VS_DISPATCH_START_GRF_SHIFT) | (brw->vs.prog_data->base.urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) | (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT)); diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c index 402d9c3..042b47d 100644 --- a/src/mesa/drivers/dri/i965/gen6_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c @@ -69,7 +69,8 @@ gen6_upload_wm_push_constants(struct brw_context *brw) fprintf(stderr, "WM constants:\n"); for (i = 0; i < prog_data->base.nr_params; i++) { if ((i & 7) == 0) - fprintf(stderr, "g%d: ", prog_data->first_curbe_grf + i / 8); + fprintf(stderr, "g%d: ", + prog_data->base.dispatch_grf_start_reg + i / 8); fprintf(stderr, "%8f ", constants[i]); if ((i & 7) == 7) fprintf(stderr, "\n"); @@ -174,17 +175,17 @@ upload_wm_state(struct brw_context *brw) if (min_inv_per_frag == 1) { dw5 |= GEN6_WM_8_DISPATCH_ENABLE; - dw4 |= (brw->wm.prog_data->first_curbe_grf << + dw4 |= (brw->wm.prog_data->base.dispatch_grf_start_reg << GEN6_WM_DISPATCH_START_GRF_SHIFT_0); - dw4 |= (brw->wm.prog_data->first_curbe_grf_16 << + dw4 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 << GEN6_WM_DISPATCH_START_GRF_SHIFT_2); } else - dw4 |= (brw->wm.prog_data->first_curbe_grf_16 << + dw4 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 << GEN6_WM_DISPATCH_START_GRF_SHIFT_0); } else { dw5 |= GEN6_WM_8_DISPATCH_ENABLE; - dw4 |= (brw->wm.prog_data->first_curbe_grf << + dw4 |= (brw->wm.prog_data->base.dispatch_grf_start_reg << GEN6_WM_DISPATCH_START_GRF_SHIFT_0); } diff --git a/src/mesa/drivers/dri/i965/gen7_gs_state.c b/src/mesa/drivers/dri/i965/gen7_gs_state.c index 30dfa6b..5f66bc6 100644 --- a/src/mesa/drivers/dri/i965/gen7_gs_state.c +++ b/src/mesa/drivers/dri/i965/gen7_gs_state.c @@ -110,7 +110,7 @@ upload_gs_state(struct brw_context *brw) (prog_data->urb_read_length << GEN6_GS_URB_READ_LENGTH_SHIFT) | (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT) | - (prog_data->dispatch_grf_start_reg << + (prog_data->base.dispatch_grf_start_reg << GEN6_GS_DISPATCH_START_GRF_SHIFT); /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c index 01be756..fd8a78f 100644 --- a/src/mesa/drivers/dri/i965/gen7_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c @@ -98,7 +98,7 @@ upload_vs_state(struct brw_context *brw) OUT_BATCH(0); } - OUT_BATCH((brw->vs.prog_data->base.dispatch_grf_start_reg << + OUT_BATCH((brw->vs.prog_data->base.base.dispatch_grf_start_reg << GEN6_VS_DISPATCH_START_GRF_SHIFT) | (brw->vs.prog_data->base.urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) | (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT)); diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c index 0782841..27a3f44 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c @@ -227,17 +227,17 @@ upload_ps_state(struct brw_context *brw) dw4 |= GEN7_PS_16_DISPATCH_ENABLE; if (min_inv_per_frag == 1) { dw4 |= GEN7_PS_8_DISPATCH_ENABLE; - dw5 |= (brw->wm.prog_data->first_curbe_grf << + dw5 |= (brw->wm.prog_data->base.dispatch_grf_start_reg << GEN7_PS_DISPATCH_START_GRF_SHIFT_0); - dw5 |= (brw->wm.prog_data->first_curbe_grf_16 << + dw5 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 << GEN7_PS_DISPATCH_START_GRF_SHIFT_2); } else - dw5 |= (brw->wm.prog_data->first_curbe_grf_16 << + dw5 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0); } else { dw4 |= GEN7_PS_8_DISPATCH_ENABLE; - dw5 |= (brw->wm.prog_data->first_curbe_grf << + dw5 |= (brw->wm.prog_data->base.dispatch_grf_start_reg << GEN7_PS_DISPATCH_START_GRF_SHIFT_0); } diff --git a/src/mesa/drivers/dri/i965/gen8_gs_state.c b/src/mesa/drivers/dri/i965/gen8_gs_state.c index a0f933c..446edec 100644 --- a/src/mesa/drivers/dri/i965/gen8_gs_state.c +++ b/src/mesa/drivers/dri/i965/gen8_gs_state.c @@ -76,7 +76,7 @@ gen8_upload_gs_state(struct brw_context *brw) (prog_data->urb_read_length << GEN6_GS_URB_READ_LENGTH_SHIFT) | (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT) | - (prog_data->dispatch_grf_start_reg << + (prog_data->base.dispatch_grf_start_reg << GEN6_GS_DISPATCH_START_GRF_SHIFT)); /* DW7 */ diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c index 8b8d5ea..3d6d7f0 100644 --- a/src/mesa/drivers/dri/i965/gen8_ps_state.c +++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c @@ -199,17 +199,17 @@ upload_ps_state(struct brw_context *brw) dw6 |= GEN7_PS_16_DISPATCH_ENABLE; if (min_invocations_per_fragment == 1) { dw6 |= GEN7_PS_8_DISPATCH_ENABLE; - dw7 |= (brw->wm.prog_data->first_curbe_grf << + dw7 |= (brw->wm.prog_data->base.dispatch_grf_start_reg << GEN7_PS_DISPATCH_START_GRF_SHIFT_0); - dw7 |= (brw->wm.prog_data->first_curbe_grf_16 << + dw7 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 << GEN7_PS_DISPATCH_START_GRF_SHIFT_2); } else { - dw7 |= (brw->wm.prog_data->first_curbe_grf_16 << + dw7 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0); } } else { dw6 |= GEN7_PS_8_DISPATCH_ENABLE; - dw7 |= (brw->wm.prog_data->first_curbe_grf << + dw7 |= (brw->wm.prog_data->base.dispatch_grf_start_reg << GEN7_PS_DISPATCH_START_GRF_SHIFT_0); } diff --git a/src/mesa/drivers/dri/i965/gen8_vs_state.c b/src/mesa/drivers/dri/i965/gen8_vs_state.c index 638e216a..f5e8dd3 100644 --- a/src/mesa/drivers/dri/i965/gen8_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen8_vs_state.c @@ -64,7 +64,7 @@ upload_vs_state(struct brw_context *brw) OUT_BATCH(0); } - OUT_BATCH((prog_data->dispatch_grf_start_reg << + OUT_BATCH((prog_data->base.dispatch_grf_start_reg << GEN6_VS_DISPATCH_START_GRF_SHIFT) | (prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) | (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT)); -- 2.7.4