From c0c468d562649df0f695737262b6230b7a56a4bb Mon Sep 17 00:00:00 2001 From: Thomas Preud'homme Date: Mon, 2 Jul 2018 11:22:20 +0100 Subject: [PATCH] [ARM] Update bfd's Tag_CPU_arch knowledge BFD's bfd_get_mach () function returns a bfd specific value representing the architecture of the target which is populated from the Tag_CPU_arch build attribute value of that target. Among other users of that interfacem, objdump which uses it to print the architecture version of the binary being examinated and to decide what instruction is available if run with "-m arm" via its own mapping from bfd_mach_arm_X values to feature bits available. However, both BFD and objdump's most recent known architecture is Armv5TE. When encountering a newer architecture bfd_get_mach will return bfd_mach_arm_unknown. This is unfortunate since objdump uses that value to allow all instructions on all architectures which is already what it does by default, making the "-m arm" trick useless. This patch updates BFD and objdump's knowledge of Arm architecture versions up to the latest Armv8-M Baseline and Mainline, Armv8-R and Armv8.4-A architectures. Since several architecture versions (eg. 8.X-A) share the same Tag_CPU_arch build attribute value and bfd_mach_arm values, the mapping from bfd machine value to feature bits need to return the most featureful feature bits that would yield the given bfd machine value otherwise some instruction would not disassemble under "-m arm" mode. The patch rework that mapping to make this clearer and simplify writing the mapping rules. In particular, for simplicity all FPU instructions are allowed in all cases. Finally, the patch also rewrite the cpu_arch_ver table in GAS to use the TAG_CPU_ARCH_X macros rather than hardcode their value. 2018-07-02 Thomas Preud'homme bfd/ * archures.c (bfd_mach_arm_5TEJ, bfd_mach_arm_6, bfd_mach_arm_6KZ, bfd_mach_arm_6T2, bfd_mach_arm_6K, bfd_mach_arm_7, bfd_mach_arm_6M, bfd_mach_arm_6SM, bfd_mach_arm_7EM, bfd_mach_arm_8, bfd_mach_arm_8R, bfd_mach_arm_8M_BASE, bfd_mach_arm_8M_MAIN): Define. * bfd-in2.h: Regenerate. * cpu-arm.c (arch_info_struct): Add entries for above new bfd_mach_arm values. * elf32-arm.c (bfd_arm_get_mach_from_attributes): Add Tag_CPU_arch to bfd_mach_arm mapping logic for pre Armv4 and Armv5TEJ and later architectures. Force assert failure for any new Tag_CPU_arch value. gas/ * config/tc-arm.c (cpu_arch_ver): Use symbolic TAG_CPU_ARCH macros rather than hardcode their values. ld/ * arm-dis.c (select_arm_features): Fix typo in heading comment. Allow all FPU features and add mapping from new bfd_mach_arm values to allowed CPU feature bits. opcodes/ * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in expected result. * testsuite/ld-arm/tls-descrelax-v7.d: Likewise. * testsuite/ld-arm/tls-longplt-lib.d: Likewise. * testsuite/ld-arm/tls-longplt.d: Likewise. --- bfd/ChangeLog | 13 +++++ bfd/archures.c | 13 +++++ bfd/bfd-in2.h | 13 +++++ bfd/cpu-arm.c | 41 ++++++++++------ bfd/elf32-arm.c | 32 +++++++++++++ gas/ChangeLog | 5 ++ gas/config/tc-arm.c | 84 ++++++++++++++++----------------- ld/ChangeLog | 6 +++ ld/testsuite/ld-arm/tls-descrelax-be8.d | 2 +- ld/testsuite/ld-arm/tls-descrelax-v7.d | 2 +- ld/testsuite/ld-arm/tls-longplt-lib.d | 2 +- ld/testsuite/ld-arm/tls-longplt.d | 2 +- opcodes/ChangeLog | 8 ++++ opcodes/arm-dis.c | 71 +++++++++++++++++++--------- 14 files changed, 213 insertions(+), 81 deletions(-) diff --git a/bfd/ChangeLog b/bfd/ChangeLog index a4ee933..96d7a4d 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,5 +1,18 @@ 2018-07-02 Thomas Preud'homme + * archures.c (bfd_mach_arm_5TEJ, bfd_mach_arm_6, bfd_mach_arm_6KZ, + bfd_mach_arm_6T2, bfd_mach_arm_6K, bfd_mach_arm_7, bfd_mach_arm_6M, + bfd_mach_arm_6SM, bfd_mach_arm_7EM, bfd_mach_arm_8, bfd_mach_arm_8R, + bfd_mach_arm_8M_BASE, bfd_mach_arm_8M_MAIN): Define. + * bfd-in2.h: Regenerate. + * cpu-arm.c (arch_info_struct): Add entries for above new + bfd_mach_arm values. + * elf32-arm.c (bfd_arm_get_mach_from_attributes): Add Tag_CPU_arch to + bfd_mach_arm mapping logic for pre Armv4 and Armv5TEJ and later + architectures. Force assert failure for any new Tag_CPU_arch value. + +2018-07-02 Thomas Preud'homme + * doc/bfdint.texi: Use command-line consistently when used in a compount word. * doc/bfdsumm.texi: Likewise. diff --git a/bfd/archures.c b/bfd/archures.c index 3af7ddd..282e983 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -326,6 +326,19 @@ DESCRIPTION .#define bfd_mach_arm_ep9312 11 .#define bfd_mach_arm_iWMMXt 12 .#define bfd_mach_arm_iWMMXt2 13 +.#define bfd_mach_arm_5TEJ 14 +.#define bfd_mach_arm_6 15 +.#define bfd_mach_arm_6KZ 16 +.#define bfd_mach_arm_6T2 17 +.#define bfd_mach_arm_6K 18 +.#define bfd_mach_arm_7 19 +.#define bfd_mach_arm_6M 20 +.#define bfd_mach_arm_6SM 21 +.#define bfd_mach_arm_7EM 22 +.#define bfd_mach_arm_8 23 +.#define bfd_mach_arm_8R 24 +.#define bfd_mach_arm_8M_BASE 25 +.#define bfd_mach_arm_8M_MAIN 26 . bfd_arch_nds32, {* Andes NDS32. *} .#define bfd_mach_n1 1 .#define bfd_mach_n1h 2 diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index f53dbb5..93745bd 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -2197,6 +2197,19 @@ enum bfd_architecture #define bfd_mach_arm_ep9312 11 #define bfd_mach_arm_iWMMXt 12 #define bfd_mach_arm_iWMMXt2 13 +#define bfd_mach_arm_5TEJ 14 +#define bfd_mach_arm_6 15 +#define bfd_mach_arm_6KZ 16 +#define bfd_mach_arm_6T2 17 +#define bfd_mach_arm_6K 18 +#define bfd_mach_arm_7 19 +#define bfd_mach_arm_6M 20 +#define bfd_mach_arm_6SM 21 +#define bfd_mach_arm_7EM 22 +#define bfd_mach_arm_8 23 +#define bfd_mach_arm_8R 24 +#define bfd_mach_arm_8M_BASE 25 +#define bfd_mach_arm_8M_MAIN 26 bfd_arch_nds32, /* Andes NDS32. */ #define bfd_mach_n1 1 #define bfd_mach_n1h 2 diff --git a/bfd/cpu-arm.c b/bfd/cpu-arm.c index c6682d4..4ef409b 100644 --- a/bfd/cpu-arm.c +++ b/bfd/cpu-arm.c @@ -129,20 +129,33 @@ scan (const struct bfd_arch_info *info, const char *string) static const bfd_arch_info_type arch_info_struct[] = { - N (bfd_mach_arm_2, "armv2", FALSE, & arch_info_struct[1]), - N (bfd_mach_arm_2a, "armv2a", FALSE, & arch_info_struct[2]), - N (bfd_mach_arm_3, "armv3", FALSE, & arch_info_struct[3]), - N (bfd_mach_arm_3M, "armv3m", FALSE, & arch_info_struct[4]), - N (bfd_mach_arm_4, "armv4", FALSE, & arch_info_struct[5]), - N (bfd_mach_arm_4T, "armv4t", FALSE, & arch_info_struct[6]), - N (bfd_mach_arm_5, "armv5", FALSE, & arch_info_struct[7]), - N (bfd_mach_arm_5T, "armv5t", FALSE, & arch_info_struct[8]), - N (bfd_mach_arm_5TE, "armv5te", FALSE, & arch_info_struct[9]), - N (bfd_mach_arm_XScale, "xscale", FALSE, & arch_info_struct[10]), - N (bfd_mach_arm_ep9312, "ep9312", FALSE, & arch_info_struct[11]), - N (bfd_mach_arm_iWMMXt, "iwmmxt", FALSE, & arch_info_struct[12]), - N (bfd_mach_arm_iWMMXt2, "iwmmxt2", FALSE, & arch_info_struct[13]), - N (bfd_mach_arm_unknown, "arm_any", FALSE, NULL) + N (bfd_mach_arm_2, "armv2", FALSE, & arch_info_struct[1]), + N (bfd_mach_arm_2a, "armv2a", FALSE, & arch_info_struct[2]), + N (bfd_mach_arm_3, "armv3", FALSE, & arch_info_struct[3]), + N (bfd_mach_arm_3M, "armv3m", FALSE, & arch_info_struct[4]), + N (bfd_mach_arm_4, "armv4", FALSE, & arch_info_struct[5]), + N (bfd_mach_arm_4T, "armv4t", FALSE, & arch_info_struct[6]), + N (bfd_mach_arm_5, "armv5", FALSE, & arch_info_struct[7]), + N (bfd_mach_arm_5T, "armv5t", FALSE, & arch_info_struct[8]), + N (bfd_mach_arm_5TE, "armv5te", FALSE, & arch_info_struct[9]), + N (bfd_mach_arm_XScale, "xscale", FALSE, & arch_info_struct[10]), + N (bfd_mach_arm_ep9312, "ep9312", FALSE, & arch_info_struct[11]), + N (bfd_mach_arm_iWMMXt, "iwmmxt", FALSE, & arch_info_struct[12]), + N (bfd_mach_arm_iWMMXt2, "iwmmxt2", FALSE, & arch_info_struct[13]), + N (bfd_mach_arm_5TEJ, "armv5tej", FALSE, & arch_info_struct[14]), + N (bfd_mach_arm_6, "armv6", FALSE, & arch_info_struct[15]), + N (bfd_mach_arm_6KZ, "armv6kz", FALSE, & arch_info_struct[16]), + N (bfd_mach_arm_6T2, "armv6t2", FALSE, & arch_info_struct[17]), + N (bfd_mach_arm_6K, "armv6k", FALSE, & arch_info_struct[18]), + N (bfd_mach_arm_7, "armv7", FALSE, & arch_info_struct[19]), + N (bfd_mach_arm_6M, "armv6-m", FALSE, & arch_info_struct[20]), + N (bfd_mach_arm_6SM, "armv6s-m", FALSE, & arch_info_struct[21]), + N (bfd_mach_arm_7EM, "armv7e-m", FALSE, & arch_info_struct[22]), + N (bfd_mach_arm_8, "armv8-a", FALSE, & arch_info_struct[23]), + N (bfd_mach_arm_8R, "armv8-r", FALSE, & arch_info_struct[24]), + N (bfd_mach_arm_8M_BASE, "armv8-m.base", FALSE, & arch_info_struct[25]), + N (bfd_mach_arm_8M_MAIN, "armv8-m.main", FALSE, & arch_info_struct[26]), + N (bfd_mach_arm_unknown, "arm_any", FALSE, NULL) }; const bfd_arch_info_type bfd_arm_arch = diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c index 870111b..b21901c 100644 --- a/bfd/elf32-arm.c +++ b/bfd/elf32-arm.c @@ -13642,6 +13642,7 @@ bfd_arm_get_mach_from_attributes (bfd * abfd) switch (arch) { + case TAG_CPU_ARCH_PRE_V4: return bfd_mach_arm_3M; case TAG_CPU_ARCH_V4: return bfd_mach_arm_4; case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T; case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T; @@ -13679,7 +13680,38 @@ bfd_arm_get_mach_from_attributes (bfd * abfd) return bfd_mach_arm_5TE; } + case TAG_CPU_ARCH_V5TEJ: + return bfd_mach_arm_5TEJ; + case TAG_CPU_ARCH_V6: + return bfd_mach_arm_6; + case TAG_CPU_ARCH_V6KZ: + return bfd_mach_arm_6KZ; + case TAG_CPU_ARCH_V6T2: + return bfd_mach_arm_6T2; + case TAG_CPU_ARCH_V6K: + return bfd_mach_arm_6K; + case TAG_CPU_ARCH_V7: + return bfd_mach_arm_7; + case TAG_CPU_ARCH_V6_M: + return bfd_mach_arm_6M; + case TAG_CPU_ARCH_V6S_M: + return bfd_mach_arm_6SM; + case TAG_CPU_ARCH_V7E_M: + return bfd_mach_arm_7EM; + case TAG_CPU_ARCH_V8: + return bfd_mach_arm_8; + case TAG_CPU_ARCH_V8R: + return bfd_mach_arm_8R; + case TAG_CPU_ARCH_V8M_BASE: + return bfd_mach_arm_8M_BASE; + case TAG_CPU_ARCH_V8M_MAIN: + return bfd_mach_arm_8M_MAIN; + default: + /* Force entry to be added for any new known Tag_CPU_arch value. */ + BFD_ASSERT (arch > MAX_TAG_CPU_ARCH); + + /* Unknown Tag_CPU_arch value. */ return bfd_mach_arm_unknown; } } diff --git a/gas/ChangeLog b/gas/ChangeLog index 9a28648..47fa7ae 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,10 @@ 2018-07-02 Thomas Preud'homme + * config/tc-arm.c (cpu_arch_ver): Use symbolic TAG_CPU_ARCH macros + rather than hardcode their values. + +2018-07-02 Thomas Preud'homme + * NEWS: Use command-line consistently when used in a compount word. * doc/as.texi: Likewise. * doc/c-aarch64.texi: Likewise. diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 6a9a655..ef814ff 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -26984,30 +26984,30 @@ typedef struct stable when new architectures are added. */ static const cpu_arch_ver_table cpu_arch_ver[] = { - {0, ARM_ARCH_V1}, - {0, ARM_ARCH_V2}, - {0, ARM_ARCH_V2S}, - {0, ARM_ARCH_V3}, - {0, ARM_ARCH_V3M}, - {1, ARM_ARCH_V4xM}, - {1, ARM_ARCH_V4}, - {2, ARM_ARCH_V4TxM}, - {2, ARM_ARCH_V4T}, - {3, ARM_ARCH_V5xM}, - {3, ARM_ARCH_V5}, - {3, ARM_ARCH_V5TxM}, - {3, ARM_ARCH_V5T}, - {4, ARM_ARCH_V5TExP}, - {4, ARM_ARCH_V5TE}, - {5, ARM_ARCH_V5TEJ}, - {6, ARM_ARCH_V6}, - {7, ARM_ARCH_V6Z}, - {7, ARM_ARCH_V6KZ}, - {9, ARM_ARCH_V6K}, - {8, ARM_ARCH_V6T2}, - {8, ARM_ARCH_V6KT2}, - {8, ARM_ARCH_V6ZT2}, - {8, ARM_ARCH_V6KZT2}, + {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V1}, + {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2}, + {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2S}, + {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3}, + {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3M}, + {TAG_CPU_ARCH_V4, ARM_ARCH_V4xM}, + {TAG_CPU_ARCH_V4, ARM_ARCH_V4}, + {TAG_CPU_ARCH_V4T, ARM_ARCH_V4TxM}, + {TAG_CPU_ARCH_V4T, ARM_ARCH_V4T}, + {TAG_CPU_ARCH_V5T, ARM_ARCH_V5xM}, + {TAG_CPU_ARCH_V5T, ARM_ARCH_V5}, + {TAG_CPU_ARCH_V5T, ARM_ARCH_V5TxM}, + {TAG_CPU_ARCH_V5T, ARM_ARCH_V5T}, + {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TExP}, + {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TE}, + {TAG_CPU_ARCH_V5TEJ, ARM_ARCH_V5TEJ}, + {TAG_CPU_ARCH_V6, ARM_ARCH_V6}, + {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6Z}, + {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6KZ}, + {TAG_CPU_ARCH_V6K, ARM_ARCH_V6K}, + {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6T2}, + {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KT2}, + {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6ZT2}, + {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KZT2}, /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as always selected build attributes to match those of ARMv6-M @@ -27016,24 +27016,24 @@ static const cpu_arch_ver_table cpu_arch_ver[] = would be selected when fully respecting chronology of architectures. It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and move them before ARMv7 architectures. */ - {11, ARM_ARCH_V6M}, - {12, ARM_ARCH_V6SM}, - - {10, ARM_ARCH_V7}, - {10, ARM_ARCH_V7A}, - {10, ARM_ARCH_V7R}, - {10, ARM_ARCH_V7M}, - {10, ARM_ARCH_V7VE}, - {13, ARM_ARCH_V7EM}, - {14, ARM_ARCH_V8A}, - {14, ARM_ARCH_V8_1A}, - {14, ARM_ARCH_V8_2A}, - {14, ARM_ARCH_V8_3A}, - {16, ARM_ARCH_V8M_BASE}, - {17, ARM_ARCH_V8M_MAIN}, - {15, ARM_ARCH_V8R}, - {14, ARM_ARCH_V8_4A}, - {-1, ARM_ARCH_NONE} + {TAG_CPU_ARCH_V6_M, ARM_ARCH_V6M}, + {TAG_CPU_ARCH_V6S_M, ARM_ARCH_V6SM}, + + {TAG_CPU_ARCH_V7, ARM_ARCH_V7}, + {TAG_CPU_ARCH_V7, ARM_ARCH_V7A}, + {TAG_CPU_ARCH_V7, ARM_ARCH_V7R}, + {TAG_CPU_ARCH_V7, ARM_ARCH_V7M}, + {TAG_CPU_ARCH_V7, ARM_ARCH_V7VE}, + {TAG_CPU_ARCH_V7E_M, ARM_ARCH_V7EM}, + {TAG_CPU_ARCH_V8, ARM_ARCH_V8A}, + {TAG_CPU_ARCH_V8, ARM_ARCH_V8_1A}, + {TAG_CPU_ARCH_V8, ARM_ARCH_V8_2A}, + {TAG_CPU_ARCH_V8, ARM_ARCH_V8_3A}, + {TAG_CPU_ARCH_V8M_BASE, ARM_ARCH_V8M_BASE}, + {TAG_CPU_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN}, + {TAG_CPU_ARCH_V8R, ARM_ARCH_V8R}, + {TAG_CPU_ARCH_V8, ARM_ARCH_V8_4A}, + {-1, ARM_ARCH_NONE} }; /* Set an attribute if it has not already been set by the user. */ diff --git a/ld/ChangeLog b/ld/ChangeLog index 399ea0a..31959a7 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,5 +1,11 @@ 2018-07-02 Thomas Preud'homme + * arm-dis.c (select_arm_features): Fix typo in heading comment. Allow + all FPU features and add mapping from new bfd_mach_arm values to + allowed CPU feature bits. + +2018-07-02 Thomas Preud'homme + * NEWS: Use command-line consistently when used in a compount word. * ld.texinfo: Likewise. * ldint.texinfo: Likewise. diff --git a/ld/testsuite/ld-arm/tls-descrelax-be8.d b/ld/testsuite/ld-arm/tls-descrelax-be8.d index 1b2159c..90a9633 100644 --- a/ld/testsuite/ld-arm/tls-descrelax-be8.d +++ b/ld/testsuite/ld-arm/tls-descrelax-be8.d @@ -1,5 +1,5 @@ .*: file format elf32-.* -architecture: arm, flags 0x[0-9a-f]+: +architecture: armv7, flags 0x[0-9a-f]+: EXEC_P, HAS_SYMS, D_PAGED start address 0x[0-9a-f]+ diff --git a/ld/testsuite/ld-arm/tls-descrelax-v7.d b/ld/testsuite/ld-arm/tls-descrelax-v7.d index 1b2159c..90a9633 100644 --- a/ld/testsuite/ld-arm/tls-descrelax-v7.d +++ b/ld/testsuite/ld-arm/tls-descrelax-v7.d @@ -1,5 +1,5 @@ .*: file format elf32-.* -architecture: arm, flags 0x[0-9a-f]+: +architecture: armv7, flags 0x[0-9a-f]+: EXEC_P, HAS_SYMS, D_PAGED start address 0x[0-9a-f]+ diff --git a/ld/testsuite/ld-arm/tls-longplt-lib.d b/ld/testsuite/ld-arm/tls-longplt-lib.d index 29b52fe..ad34c55 100644 --- a/ld/testsuite/ld-arm/tls-longplt-lib.d +++ b/ld/testsuite/ld-arm/tls-longplt-lib.d @@ -1,5 +1,5 @@ .*: file format elf32-.*arm -architecture: arm, flags 0x00000150: +architecture: armv6t2, flags 0x00000150: HAS_SYMS, DYNAMIC, D_PAGED start address 0x.* diff --git a/ld/testsuite/ld-arm/tls-longplt.d b/ld/testsuite/ld-arm/tls-longplt.d index afa6b06..0664672 100644 --- a/ld/testsuite/ld-arm/tls-longplt.d +++ b/ld/testsuite/ld-arm/tls-longplt.d @@ -1,5 +1,5 @@ .*: file format elf32-.*arm -architecture: arm, flags 0x00000112: +architecture: armv6t2, flags 0x00000112: EXEC_P, HAS_SYMS, D_PAGED start address 0x.* diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index c2d979a..fdc0e44 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +2018-07-02 Thomas Preud'homme + + * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in + expected result. + * testsuite/ld-arm/tls-descrelax-v7.d: Likewise. + * testsuite/ld-arm/tls-longplt-lib.d: Likewise. + * testsuite/ld-arm/tls-longplt.d: Likewise. + 2018-06-29 Tamar Christina PR binutils/23192 diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 6f93cfd..da28837 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -6387,7 +6387,7 @@ mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info, /* Given a bfd_mach_arm_XXX value, this function fills in the fields of the supplied arm_feature_set structure with bitmasks indicating - the support base architectures and coprocessor extensions. + the supported base architectures and coprocessor extensions. FIXME: This could more efficiently implemented as a constant array, although it would also be less robust. */ @@ -6396,40 +6396,69 @@ static void select_arm_features (unsigned long mach, arm_feature_set * features) { + arm_feature_set arch_fset; + const arm_feature_set fpu_any = FPU_ANY; + #undef ARM_SET_FEATURES #define ARM_SET_FEATURES(FSET) \ { \ const arm_feature_set fset = FSET; \ - arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \ - ARM_MERGE_FEATURE_SETS (*features, tmp, fset); \ + arch_fset = fset; \ } + /* When several architecture versions share the same bfd_mach_arm_XXX value + the most featureful is chosen. */ switch (mach) { - case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break; - case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break; - case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break; - case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break; - case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break; - case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break; - case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break; - case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break; - case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break; - case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break; + case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break; + case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break; + case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break; + case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break; + case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break; + case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break; + case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break; + case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break; + case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break; + case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break; case bfd_mach_arm_ep9312: - ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T, - ARM_CEXT_MAVERICK | FPU_MAVERICK)); + ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T, + ARM_CEXT_MAVERICK | FPU_MAVERICK)); break; - case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break; - case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break; - /* If the machine type is unknown allow all - architecture types and all extensions. */ - case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break; + case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break; + case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break; + case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break; + case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break; + case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break; + case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break; + case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break; + case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break; + case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break; + case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break; + case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break; + case bfd_mach_arm_8: + { + /* Add bits for extensions that Armv8.4-A recognizes. */ + arm_feature_set armv8_4_ext_fset + = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML); + ARM_SET_FEATURES (ARM_ARCH_V8_4A); + ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_4_ext_fset); + break; + } + case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break; + case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break; + case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break; + /* If the machine type is unknown allow all architecture types and all + extensions. */ + case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break; default: abort (); } - #undef ARM_SET_FEATURES + + /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch + and thus on bfd_mach_arm_XXX value. Therefore for a given + bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */ + ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any); } -- 2.7.4