From c0692c08ee2ec60bb6bdd9dbe1b2c79235ce6f35 Mon Sep 17 00:00:00 2001 From: Philip Reames Date: Wed, 30 Nov 2022 10:44:51 -0800 Subject: [PATCH] [RISCV] Adjust code to fallthrough to a single adjustReg callsite [nfc] Note that we have to now pass alignment to that callsite because the wrapper previously did that for us for fixed offsets. --- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index dba3fc9..e5df886 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -332,24 +332,26 @@ void RISCVFrameLowering::adjustStackForRVV(MachineFunction &MF, const Register SPReg = getSPReg(STI); // Optimize compile time offset case + StackOffset Offset = StackOffset::getScalable(Amount); if (STI.getRealMinVLen() == STI.getRealMaxVLen()) { // 1. Multiply the number of v-slots by the (constant) length of register const int64_t VLENB = STI.getRealMinVLen() / 8; assert(Amount % 8 == 0 && "Reserve the stack by the multiple of one vector size."); const int64_t NumOfVReg = Amount / 8; - const int64_t Offset = NumOfVReg * VLENB; - if (!isInt<32>(Offset)) { + const int64_t FixedOffset = NumOfVReg * VLENB; + if (!isInt<32>(FixedOffset)) { report_fatal_error( "Frame size outside of the signed 32-bit range not supported"); } - adjustReg(MBB, MBBI, DL, SPReg, SPReg, Offset, Flag); - return; + Offset = StackOffset::getFixed(FixedOffset); } const RISCVRegisterInfo &RI = *STI.getRegisterInfo(); - RI.adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getScalable(Amount), - Flag, None); + // We must keep the stack pointer aligned through any intermediate + // updates. + RI.adjustReg(MBB, MBBI, DL, SPReg, SPReg, Offset, + Flag, getStackAlign()); } void RISCVFrameLowering::emitPrologue(MachineFunction &MF, -- 2.7.4